Just FYI.
This test is just bogus and fixing it might be simple as using -fsanitize=undefined to check at runtime there is no undefined behavior being hit.
In this case even if we do the comparison in `signed` and do the negate in `unsigned` types. we can still remove the negate in this case since we know the only value that will be still negative in that branch is LONG_MIN. So my patch just simplifies the inner comparison to that instead of `a < 0` and then be able to remove the neg.
Someone else will have to fix the testcase since it is a testcase issue ...
________________________________________
From: ci_notify(a)linaro.org <ci_notify(a)linaro.org>
Sent: Friday, September 1, 2023 3:07 PM
To: Andrew Pinski
Subject: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions
External Email
----------------------------------------------------------------------
Dear contributor, our automatic CI has detected problems related to your patch(es).
Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list.
In CI config tcwg_gcc_check/master-aarch64 after:
| 2 patches in gcc
| Patchwork URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.sourceware.o…
| 504821491ff VR-VALUES: Rewrite test_for_singularity using range_op_handler
| f6d1540c3e0 VR-VALUES: Rename op0/op1 to op1/op2 for test_for_singularity
| ... applied on top of baseline commit:
| b0d75f7d3bb libstdc++: Fix debug-mode tests for constexpr algorithms
FAIL: 1 regressions
regressions.sum:
=== gcc tests ===
Running gcc:gcc.target/aarch64/aarch64.exp ...
FAIL: gcc.target/aarch64/vnegd_s64.c scan-assembler-times neg\\tx[0-9]+, x[0-9]+ 1
=== Results Summary ===
-----------------8<--------------------------8<--------------------------8<--------------------------
The information below can be used to reproduce a debug environment:
Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- code review:
+ RTH's linux-user ESR signal frame patchset
+ iMX6/7 cleanup patchset
+ some other minor bits and pieces
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
* SETG* instructions (memset + MTE tag setting) implemented and
given some basic testing
-- PMM
Hi Jan,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I am having some trouble to reproduce it outside
our CI environment, but it has been hitting this issues consistently
and it does seems related to your patch.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_bootstrap_build--master-aarch64-bootstrap_pr…
Hi Richard,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that for
test_copy_lane_f32, test_copy_lane_s32, test_copy_lane_u32, gcc
is now generating zip1 instead of a ins; which does not seem
fully correct.
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_cross_check_gcc--master-aarch64-build/91…
Hello,
# TCWG CI
- GCC regression GNU-884: Prathamesh confirmed that the new generated
code is better so I posted a patch adjusting the testcase.
- GCC regression GNU-885: Confirmed that the problem is still present in
trunk as of commit 829c0c06fe7b from yesterday, so opened bugzilla
111125 and copied the patch author. He fixed the regression.
- Posted Gerrit review request to increase timeout for GDB check jobs to
accommodate longer times for Armv8l builds.
# GDB Upstream
- Reviewed v4 of Luis' patch series adding SME support to GDB and
gdbserver.
--
Thiago
Hi Andrew,
Your patch caused a regression [1] on aarch64-linux-gnu. Would you
please investigate? I did a quick analysis and it seems that the
expected 18 for aarch64 is now 17:
$ grep "Jumps threaded" a-ssa-dom-thread-7.c.197t.thread2
Jumps threaded: 17
Let me know if you need any assistance in reproducing these.
Thanks!
[1] https://ci.linaro.org/job/tcwg_gnu_native_check_gcc--master-aarch64-build/5…
Hi Richard,
Your patch below ICEs on aarch64-linux-gnu. Should reproduce easily on native or cross aarch64-linux-gnu build.
Let me know if you need any assistance in reproducing this.
Thanks,
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 24, 2023, at 22:03, ci_notify(a)linaro.org wrote:
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it. If you have any questions, please
> follow up on linaro-toolchain(a)lists.linaro.org mailing list.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | commit a1558e9ad856938f165f838733955b331ebbec09
> | Author: Richard Biener <rguenther(a)suse.de>
> | Date: Wed Aug 23 14:28:26 2023 +0200
> |
> | tree-optimization/111115 - SLP of masked stores
> |
> | The following adds the capability to do SLP on .MASK_STORE, I do not
> | plan to add interleaving support.
> |
> | PR tree-optimization/111115
> | ... 21 lines of the commit log omitted.
>
> FAIL: 6 regressions
>
> regressions.sum:
> === gcc tests ===
>
> Running gcc:gcc.target/aarch64/sve/aarch64-sve.exp ...
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (internal compiler error: in get_group_load_store_type, at tree-vect-stmts.cc:2121)
> FAIL: gcc.target/aarch64/sve/mask_struct_store_4.c (test for excess errors)
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2b\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2d\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2h\\t.z[0-9]
> UNRESOLVED: gcc.target/aarch64/sve/mask_struct_store_4.c scan-assembler-not \\tst2w\\t.z[0-9]
>
> ... and 1 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/artifact…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/856/artifact…
>
> Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/…
>
> Full commit : https://github.com/gcc-mirror/gcc/commit/a1558e9ad856938f165f838733955b331e…
>
> Latest bug report status : https://linaro.atlassian.net/browse/GNU-893
>
> List of configurations that regressed due to this commit :
> * tcwg_gcc_check
> ** master-aarch64
> *** FAIL: 6 regressions
> *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/857/
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- code review:
+ Xilinx Versal CFI support series
+ v2 of RTH's Cortex-A710 series
- a few more -Wvla patches
- put together and sent the first arm pullreq for the 8.2 cycle
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- FEAT_MOPS:
+ updated to use a refactoring suggested by RTH
+ started looking at SETG operation (memset with MTE tag setting)
-- PMM
Hi Julian,
Your patch series causes regressions on aarch64-linux-gnu. Would you please investigate?
Let me know if you need any assistance in reproducing these.
Thanks!
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 19, 2023, at 09:32, ci_notify(a)linaro.org wrote:
>
> [Linaro-TCWG-CI] FAIL: 10 regressions after gcc commit: 5 commits in gcc
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | gcc commits:
> | dce6c135fb52fd631c2fc82d8048d32ce41ece21 OpenMP/OpenACC: Reorganise OMP map clause handling in gimplify.cc
> | dd49dd178e3eac8e9925baa3d71325d8d5f69215 OpenMP/OpenACC: Unordered/non-constant component offset runtime diagnostic
> | bd5a53e6b47907d05672cbb603af363a665b45a4 OpenMP: Pointers and member mappings
> | 4e0359d8a659c8abdca3297fc9b0e20ff89f7f82 OpenMP/OpenACC: Rework clause expansion and nested struct handling
> | a855174e5461d2b423af7f892fd31dfb10ce09ec OpenMP/OpenACC: Reindent TO/FROM/_CACHE_ stanza in {c_}finish_omp_clause
>
> FAIL: 10 regressions
>
> regressions.sum:
> === libgomp tests ===
>
> Running libgomp:libgomp.c++/c++.exp ...
> FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test
> FAIL: libgomp.c++/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test
>
> Running libgomp:libgomp.c/c.exp ...
> FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-2.c output pattern test
> FAIL: libgomp.c/../libgomp.c-c++-common/map-arrayofstruct-3.c output pattern test
>
> ... and 9 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1593/art…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact…
Hi Manos,
New tests in your patch [1] fail on aarch64-linux-gnu build in our CI. Would you please investigate why? Testing logs are at [2].
[1] https://patchwork.sourceware.org/project/gcc/patch/20230818074943.41754-1-m…
[2] https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art…
--
Maxim Kuvyrkov
https://www.linaro.org
> On Aug 19, 2023, at 08:37, ci_notify(a)linaro.org wrote:
>
> [Linaro-TCWG-CI] FAIL: 6 regressions after gcc commit: basepoints/gcc-14-3331-gcddc26e0274 aarch64: Fine-grained ldp and stp policies with test-cases.
>
> Dear contributor, our automatic CI has detected problems related to your patch.
> Please find below some details about it.
>
> In CI config tcwg_gcc_check/master-aarch64 after:
>
> | commit cddc26e0274b51e775929e497f89d203211689d2
> | Author: Manos Anagnostakis <manos.anagnostakis(a)vrull.eu>
> | Date: Fri Aug 18 10:49:43 2023 +0300
> |
> | aarch64: Fine-grained ldp and stp policies with test-cases.
> |
> | This patch implements the following TODO in gcc/config/aarch64/aarch64.cc
> | to provide the requested behaviour for handling ldp and stp:
> |
> | /* Allow the tuning structure to disable LDP instruction formation
> | ... 47 lines of the commit log omitted.
>
> FAIL: 6 regressions
>
> regressions.sum:
> === gcc tests ===
>
> Running gcc:gcc.target/aarch64/aarch64.exp ...
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 1
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 3
> FAIL: gcc.target/aarch64/ldp_aligned.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 3
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tq[0-9]+, q[0-9] 2
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tw[0-9]+, w[0-9] 6
> FAIL: gcc.target/aarch64/ldp_always.c scan-assembler-times ldp\tx[0-9]+, x[0-9] 6
>
> ... and 1 more entries
>
>
>
> -----------------8<--------------------------8<--------------------------8<--------------------------
> The information below can be used to reproduce a debug environment:
>
> Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/art…
> Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/836/artifact…
>
> Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/gcc/sha1/…
>
> Full commit : https://github.com/gcc-mirror/gcc/commit/cddc26e0274b51e775929e497f89d20321…
>
> Latest bug report status : https://linaro.atlassian.net/browse/GNU-692
>
> List of configurations that regressed due to this commit :
> * tcwg_gcc_check
> ** master-aarch64
> *** FAIL: 6 regressions
> *** https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/1602/
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Continued working on new approach to support changing SVE vector
length in remote debugging.
# TCWG CI
- Analysed GCC regression GNU-880 which is actually an XFAIL → XPASS so
I sent a patch removing the xfail annotation.
- Analysed GCC regression GNU-881. The problem is that we don't have
Python in the ABE sysroot so a new Python GCC plugin testcase fails to
build. Sent a patch to detect that situation and mark the test as
unsupported. It was committed upstream.
- Tested a couple of new versions of a GDB mailing list patch to see if
it fixed the failure reported by the precommit CI. Reported results to
patch author.
- Fixed silly mistake spotted by Laurent in ABE Gerrit requests to use
TIMEOUTFACTOR for DejaGnu testsuites. Adjusted it to not use the
factor in GDB on armhf and sent new version for review.
- Reviewed a couple of Gerrit requests.
--
Thiago
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- sent out another couple of "avoid VLA" patches
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- managed to write some first-pass code for the MTE checks for
FEAT_MOPS memset operations. Got something together enough to
send to RTH for some pre-review before I roll the approach out
to the other insns.
-- PMM
Hello,
# [GNU-767] Support changing SVE vector length in remote debugging
- Returned to implementing support for changing SVE vector length in
remote debugging. The patch series I sent earlier this year used an
approach that some maintainers weren't enthusiastic about (modifying
the Remote Serial Protocol to request XML target descriptions). Now
trying the approach they suggested, which is to extend target
descriptions to support expressing vector registers whose length is
given by the contents of another register.
# TCWG CI
- Following Maxim's suggestion, sent and merged Gerrit review requests
to increase chance of tcwg_gdb_check jobs to be faster at detecting
new or newly expired flaky tests:
- 45151: tcwg_gdb: Increase job frequency
- 45152: round-robin.sh (build_abe): Increase time to re-detect GDB
flaky tests
- Implemented change in ABE to support glibc's TIMEOUTFACTOR environment
variable for DejaGnu testsuites. Testing on armv8l and aarch64.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- code review, notably:
+ RTH's setnegcond series
+ Jean-Philippe's fixes for various FEAT_RME bugs
+ Akihiko's series to make KVM '-machine none' not default to 40 bits
of IPA space if the host doesn't supoprt that (like the Apple CPUs)
- sent a patch to catch the illegal exception return case from
EL3 with bad SCR_EL3.{NSE,NS}
- respin and resend of ptw cleanup patchset
- tidied another 'BiteSizedTask' entry into a gitlab issue
- went back to an old minor cleanup task: getting rid of the
last dozen or so uses of variable-length arrays in the codebase
(so we can enforce not using them in the compiler, and avoid
unchecked-on-stack-allocation security bugs). Sent patches to
zap a few more.
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- thinking a bit more about FEAT_MOPS and MTE checks, but ultimately
not much progress: didn't find enough hours with a sufficiently
alert mind...
-- PMM
Hello,
# TCWG CI
- Implemented increasing testsuite timeout for each testsuite try in GDB
check jobs. Sent a Gerrit review request for it but then found out that
it makes armhf jobs take a lot longer, so abandoned it.
# Community
- Finished reviewing SME patches for GDB and gdbserver.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- some bits and pieces for release
- code review, notably:
+ raspberry pi 4 support patchseries (a big 44-patch set)
+ Xilinx Versal CFI support patches
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- more work on FEAT_MOPS: tested my memset implementation, and
fixed various bugs. Still no MTE tag checking support.
-- PMM
Hello,
# TCWG CI
- CI Babysitting: Worked on two regressions detected at the end of last
week.
- Enabled precommit testing for GDB patches.
# Misc
- Reviewing SME patches for GDB and gdbserver.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- release related stuff: handling merge requests, etc (now passed
back to RTH again)
- sent some patches for a few easy coverity issues
- worked through some code review (in particular some patches
from new contributors)
- created a gitlab "bite sized task" issue that better explains
and has more detail on the "convert from malloc to g_malloc"
suggested task for new contributors
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- a little more progress with FEAT_MOPS. I now have an untested
implementation of the memset insns which I think is complete
except for MTE tag checking
-- PMM
Hello,
# TCWG CI
- Babysat the CI: Investigated 9 regressions in GCC, 2 in GDB, 1 in LLVM
and 1 in glibc. Reported 4 in GCC (GNU-855, GNU-857, GNU-858 and
GNU-859). 3 of which are fixed and another has a tentative fix.
- Reviewed a couple of Gerrit requests.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- fixed some places in our RTC device models where we were
putting a time_t or time_t offset into a 32-bit variable
- took over from RTH briefly for pullreq merge handling
- sent some patches fixing minor Coverity issues
- investigated a couple of "test case fails on big-endian host"
errors: sent patches for Sparc FPRS handling and for
the Arm SMMUv3 model
- Investigated report that our MPS2/3 M-profile models don't
have the same number of MPU regions configured as the real FPGA
images, and so you can't run the same Zephyr binary on both.
Have some preliminary patches to correct the number of regions.
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- finally got back to FEAT_MOPS work; wrote a skeleton of code
for the memset operations that's about right up to the point
where it needs to actually do the memset...
-- PMM
Hi everyone,
I'm not 100% sure whether this is a bot misconfiguration issue, but couldn't find any other source of this failure:
```
******************** TEST 'test-suite :: MultiSource/Applications/ClamAV/clamscan.test' FAILED ********************
Executable '/home/tcwg-buildbot/worker/clang-aarch64-sve-vla/test/sandbox/build/MultiSource/Applications/ClamAV/clamscan' is missing
********************
```
Link: https://lab.llvm.org/buildbot/#/builders/197/builds/8209
Would anyone be able to take a look?
Thank you :)
-Andrzej
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Progress:
* UM-2 [QEMU upstream maintainership]
- investigated and fixed a bug in page-table-walk handling of
debug accesses that was introduced by the FEAT_RME changes
- that prompted me to look at a cleanup of some of the ptw code
so that we consistently look at "which space is this walk for"
and don't carry around a parallel boolean "secure/non-secure"
that duplicates that information
- found and fixed a few other ptw bugs along the way
-- PMM
Hello,
# TCWG CI
- Changed tcwg_gnu-build.sh to apply GDB patch adding
'--with-additional-debug-dirs' option, and ABE's gdb.conf to use it.
Also changed both to add '--prefix /usr' option to GDB's configure.
Both changes to fix ld.so debug info issues in GDB testsuite runs on
armhf.
- Testing changes to validate_failures.py and jenkins-scripts to handle
empty gdb.sum.
- Reviewed a few Gerrit requests.
--
Thiago
Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
- softfreeze is next week, so spent some time putting together
a pull request, fixing the bugs which the CI tests found in
it, etc
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- now that we implement all the necessary features (excluding
some trace/profiling type stuff that is out-of-scope for
QEMU, and also FEAT_NV that we might come back to later), sent
out the patchset to define a 'neoverse-v1' CPU type for QEMU
-- PMM
Hello,
# TCWG Infrastructure
- Investigated why the CI didn't recover from empty gdb.sum, since it
was supposed to.
- Fixing validate_failures.py and tcwg_gnu-build.sh to correctly handle
empty gdb.sum.
- Fixing GDB armhf CI jobs to find distro's debug info.
# CI Babysitting
- Verified that a couple of regressions I reported last week were fixed
in trunk.
--
Thiago
Hello,
# TCWG CI — GDB
- Investigated why the GDB check jobs stopped succeeding, as reported by
Maxim. It turns there was an upstream commit (which was soon reverted)
that broke generation of the gdb.sum file and consequently our
baseline results became empty. Theoretically the CI should recover
from that but we don't deal well with this corner case. With Maxim's
help, restored the baseline and now things should be back to normal.
Will improve our scripts to avoid this trap.
# CI Babysitting
This week was my turn to baby sit the CI.
- Investigated 12 regressions in GCC and reported 3. The others were
already fixed.
- Investigated 1 regression in GDB but it wasn't actually one.
- Investigated 1 regression in QEMU but it was already fixed.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- catch up on email after a week away
- Put together some arm pull requests
- sent out draft QEMU summit minutes for review
- sent patch to avoid using the buggy __builtin_subcll in
Apple Clang 14
- sent patch fixing build error with newer xkeyboard-data
- some gardening of Coverity issue reports
Last week was KVM Forum in Brno -- here's a quick trip summary:
This year KVM Forum was a slightly smaller conference (2 days, single-track),
as we are now organizing it independently of the Linux Foundation. The
independent organization went pretty well this year (despite the slightly
awkward short notice) and the conference was very useful both for the
talks and for the hallway track.
Interesting talks (just a sampling biased to my interests):
* KVM: Arm Confidential Compute Architecture Support
Suzuki Poulose presented a summary of FEAT_RME and the CCA hardware
and software architecture, and how it's intended to fit into KVM
* KVM/arm64: Episode V - The Blob Strikes Back
Immediately following was Marc Zyngier and Oliver Upton from Google:
their talk was a pretty strong critique of the CCA software stack
architecture. Their central point is that having the RMM be "part of
the firmware" rather than "part of the hypervisor" is going to cause
a rerun of all the issues we've seen with dubious and non-upgradable
vendor code in EL3. Secondly, having the fixed API between the
hypervisor and the RMM restricts to least-common-denominator and
provides no room for experimentation and optimizations. They want an
architected way to deploy an RMM at boot time.
* Handling complex guest exits with eBPF
Will Deacon presented what he described as "conference driven
development" -- an interesting prototype of having device models in
the host kernel that are implemented in eBPF. This (in theory) gives
you the performance gains of an in-kernel device without it putting
a lot of C code onto the security boundary between the guest and host.
* Challenges Revisited in Supporting Virt CPU Hotplug on architectures
that don't Support CPU Hotplug (like ARM64)
James Morse (Arm) and Salil Mehta (Huawei) presented on CPU hotplug.
The underlying problem here remains that Arm has no hardware hotplug
handling, so there's no clear model for what hotplug on a VM should
look like. Cloud vendors have an obvious desire for the x86-style
tooling to Just Work on Arm too. The gap between "we have a prototype
that seems to work" and "upstreamable maintainable code" has not
yet been bridged, though...
* QEMU Arm CPU models and KVM
Cornelia Huck (RedHat) had a talk that was intended as a statement of
the problem rather than a proposed solution. At the moment we only
let a KVM guest see the same CPU type as the host and don't have a
mechanism for presenting a subset of features to it. KVM is about to
get support for letting the VMM define what the guest should see in
the ID registers, but how should we expose that to QEMU users without
ending up with a thousand command line sub-options to turn on and off
every architectural FEAT_FOO? And how do we deal with errata
workarounds, which the guest currently selects based on the MIDR value?
As usual, we held the QEMU Summit (an hour-long maintainer discussion
mostly about process and organizational issues) during KVM Forum. I
still need to write up the minutes for this, but they'll be published
on the qemu-devel list shortly.
thanks
-- PMM
Hi,
In binutils I need to write an offset between two symbols shifted right by 2 bits. This offset is written to the xdata section. My
code currently looks like this:
exp.X_op = O_subtract;
exp.X_add_symbol = symbol1;
exp.X_op_symbol = symbol2;
emit_expr (&exp, 2);
This works fine but obviously the result value is not shifted. Anyone have a good option is to shift the output of emit_expr at
write time?
I cannot use resolve_expression because the symbols do not have correct addresses at the time this code executes.
Any help appreciated,
Zac
Hello,
# TCWG CI — GDB
- Changed tcwg_gnu-build.sh to apply GDB testsuite patch to avoid infinite
loop in tcwg_gdb_check--master-arm jobs, while it isn't committed
upstream.
- Started investigating corrupt gdb.sum.1 file in
tcwg_gdb_check--master-arm jobs. I can't reproduce it by manually
running the CI's "make check-gdb" command line, nor by using ABE. I can
reproduce it with tcwg_gnu-build.sh though.
- Came up with validate_failures.py change to make it cope with the
corrupt gdb.sum.1 file, while the underlying cause isn't known.
Submitted the change upstream.
# TCWG Infrastructure
- Reviewed some Gerrit requests for our CI scripts.
# Misc
- Did some travel planning for Linaro Employee Meeting and GNU Tools
Cauldron.
--
Thiago
Project Orko
============
- more virtio-gpu discussion, blog post soon
Enable Arm Architecture in QEMU
===============================
- prep for KVM Forum talk
Other
=====
- various syncs
Absences
========
- KVM Forum next week
Current Review Queue
====================
TODO [RFC v2 0/6] Native Library Calls
Message-Id: <20230607164750.829586-1-fufuyqqqqqq(a)gmail.com>
=================================================================================================
TODO [PATCH] Add virtio-sound and virtio-sound-pci devices
Message-Id: <20230526204845.673031-1-manos.pitsidianakis(a)linaro.org>
==============================================================================================================================
TODO [PATCH v2 00/10] hw/virtio: Build various target-agnostic objects just once
Message-Id: <20230524093744.88442-1-philmd(a)linaro.org>
======================================================================================================================================
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Progress:
* UM-2 [QEMU upstream maintainership]
- code review (including a new board-and-devices
patchseries for a TI Tiva C devboard)
- Put together an arm pull request
- Investigated some bug reports, sent patches:
* regression in Allwinner A10 interrupt controller
* hang in icount mode on microbit with Zephyr guest
* LDG doesn't return the right values when ATA==0
- prep for next week's KVM Forum trip
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- handling review comments and rebasing of decodetree
load/store conversion
- investigating a few issues I noticed in the process
-- PMM
Hello,
# TCWG CI — GDB
- Addressed review comments and sent v2 and v3 of the patch fixing loop
in gdb.reverse/step-reverse.exp. The testcase's original author gave his
Reviewed-by, now waiting for approval by a maintainer. In the meantime,
set up our CI to apply the patch locally.
- Sent patch to the GDB mailing list implementing configure option
'--with-additional-debug-dirs' to allow building a GDB binary with a
custom install prefix but which also looks for debug info in
/usr/lib/debug. This should solve the SIGILL issue on armhf-linux in our
CI, and allow a few more tests to run on aarch64-linux.
# TCWG Infrastructure
- Reviewed some Gerrit requests related to notification and baseline
updating.
--
Thiago
Hello,
# TCWG CI — GDB
- Continued investigating issue with GDB on armhf-linux about getting
SIGILL when trying to detect shared library loading/unloading. Noticed
that the problem happens only in tests that use the distro's toolchain
(either because they're for a language we don't build in ABE gcc, or
because GDB itself is built with the distro toolchain), so the impact
isn't as widespread as I initially thought. It still frequently causes
trouble for our CI loop though. Working on a fix.
- Investigated and fixed loop in gdb.reverse/step-reverse.exp that was
causing tcwg_gdb_check--master-arm-build jobs to get stuck, as
reported by Maxim. Posted patch to the GDB mailing list.
# TCWG Infrastructure
- Reviewed Gerrit requests about testing mailing list patches in our CI.
--
Thiago
Progress (another short week, May is great this year):
* UM-2 [QEMU upstream maintainership]
- More review on some of RTH's atomics related patchsets
- Put together an arm pull request
- Sent out a call for agenda items for QEMU Summit
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- decodetree load/store conversion done, patches sent out for review.
After this I plan to go back to the FEAT_MOPS implementation
(and then do the last part of the integer A64 decodetree
conversion later in this release cycle).
-- PMM
Hello,
# TCWG CI — GDB
- Investigating issue in CI jobs where touching all C files causes GDB
to show a warning about the source being newer than the executable.
This interferes with a few GDB tests.
- Continued investigating issue with GDB on armhf-linux about getting
SIGILL when trying to detect shared library loading/unloading. Found
out that the GDB testsuite binaries are using the distro's ld.so
rather than the one built by ABE and which is the one expected to be
used. Because we don't have debuginfo installed for the distro's
ld.so, we hit the GDB bug in armhf-linux. The ld.so built by ABE has
debuginfo and would avoid hitting the issue.
# TCWG Infrastructure
- Reworked CI job to sanity check tcwg_gnu_fast_check_{gcc,gdb} and
posted new version for review.
- Reviewed some Gerrit requests for jenkins-scripts and ABE.
--
Thiago
Progress (short week, three days):
* UM-2 [QEMU upstream maintainership]
- Sent a patch fixing a bug where we broke some M-profile uses
(resulting in assertion failures) when we added v8R support
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- Implemented support for a new feature in the decodetree
generator that I need for the A64 decodetree conversion,
sent patches out for review
- More progress on A64 decodetree: loads and stores
-- PMM
Hello,
# TCWG CI — GDB
- Analysed a number of potential regressions found by our CI on
aarch64-linux and armhf-linux. They aren't exactly regressions but bug
fixes or new features that work on other arches (or perhaps whose
testcases correctly detect PASSes on other arches) but not on
aarch64-linux or armhf-linux.
- armhf-linux has an important problem where a bug with detecting shared
library loading/unloading is causing many tests to fail. The result is
that every new GDB commit that adds a test is flagged by the bisect
job. This was caused by a GDB commit from November 2022. Luis reported
it at the time and the patch author was going to look into it, but
this probably fell through the cracks. I'm investigating to understand
the problem better and provide a fix.
--
Thiago
Progress:
* UM-2 [QEMU upstream maintainership]
- Reviewed another round of RTH's patchset overhauling atomics
- Sent an arm pullreq
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- Continued with the conversion of the A64 decoder to decodetree:
have converted hints, barriers, system register insns,
exception generation, and am halfway through the loads and stores.
-- PMM
Hi,
Has anyone noticed that https://lab.llvm.org/buildbot/#/builders/198 (clang-aarch64-sve-vla-2stage<https://lab.llvm.org/buildbot/#/builders/198>) has been timing out for the past few days? "Duration" is often less than 1hr, so that's odd. And all Flang buildbots are green, so it's unlikely caused by changes to that sub-project (https://lab.llvm.org/buildbot/#/builders/198/builds/1804). Would anyone be able to take a look?
Best regards,
Andrzej
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hello,
# TCWG Infrastructure
- Reviewed a bunch of Gerrit requests for our CI scripts.
- Finished job definition to run fast_check_{gcc,gdb} jobs triggered by
new Gerrit review requests for jenkins-scripts, benchmark scripts and
ABE. Sent Gerrit review request and now working on 2nd version.
- Rebased our DejaGNU debug patches to upstream dejagnu-1.6.3, tested
result and sent Gerrit review request for it.
# TCWG CI — GDB
- Confirmed regression found by CI job¹ and mentioned by Maxim. Found
out that it was fixed upstream already².
--
Thiago
¹ https://ci.linaro.org/job/tcwg_gnu_native_check_gdb--master-aarch64-bisect/…
² https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5a6ad5c775a58367…
Progress (another short week, May is full of bank holidays :-)):
* UM-2 [QEMU upstream maintainership]
- usual background level of code review etc
- investigated a bug reported by Mozilla where people running x86 Firefox
on QEMU on Arm hardware were seeing crashes; narrowed down the cause
(aided by Mozilla kindly providing a minimal repro test case),
and Paolo produced a fix.
* QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG]
- Started looking at what is required for FEAT_MOPS (the
memcpy/memset/memmove insns), what they do and how QEMU ought
to implement them.
- The new insns are in the load/store part of the A64 instruction
space. To make this easier to do, we should really convert at
least the integer parts of the A64 decoder to decodetree (a
refactoring we've been putting off for a long time). Started on
the conversion: sent out a first 20-patch patchset that converts
the dp-immediate and branch insns.
-- PMM