VirtIO Related Work ([VIRT-366])
================================
- had a couple of HOs and internal threads to flesh out understanding
for VirtIO work
- queried VIRTIO adoption in other hypervisors Message-Id:
<87mu93vwy2.fsf(a)linaro.org> to help understanding
- need a meeting with QC/NXP to discuss their requirements and why
they need certain devices in VirtIO
- a lot of the Android focus seems to be on isolating various secure
workloads
- avoiding needing secure but un-trusted code at elevated privileges
with access to main OS
- suspect the breakdown in the card needs re-arranging
[VIRT-366] <https://projects.linaro.org/browse/VIRT-366>
Upstream Work ([VIRT-109])
==========================
- posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id:
<20200130113223.31046-10-alex.bennee(a)linaro.org>
- posted [PULL 00/19] testing and plugin updates Message-Id:
<20200226073929.28237-1-alex.bennee(a)linaro.org>
- did some debugging/diagnosis for recent slowdown of ARM emulation in
master Message-Id:
<CAPan3Wq-MVwcJQELP8n+g33CR7tsiGXQ698gA177nd2my9hWCw(a)mail.gmail.com>
- posted [PATCH v1 0/4] Fix codegen translation cache size
Message-Id: <20200226181020.19592-1-alex.bennee(a)linaro.org>
[VIRT-109] <https://projects.linaro.org/browse/VIRT-109>
Completed Reviews [3/3]
=======================
[PATCH v16 00/10] VIRTIO-IOMMU device
Message-Id: <20200214132745.23392-1-eric.auger(a)redhat.com>
- CLOSING NOTE [2020-02-26 Wed 15:37]
It's in an in-flight PR now, will play with it once it lands.
Added: <2020-02-14 Fri>
[PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns
Message-Id: <20200225143923.22297-1-peter.maydell(a)linaro.org>
[PATCH v3 0/3] Fix number of priority bits for arm boards
Message-Id: <1582537164-764-1-git-send-email-sai.pavan.boddu(a)xilinx.com>
- CLOSING NOTE [2020-02-28 Fri 17:22]
Have been pulled into target-arm next but didn't fix the
kvm-unit-test failures with priority masking as I had hopped they
would.
Added: <2020-02-25 Tue>
Absences
========
- None
Current Review Queue
====================
* [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU
Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com>
Added: <2020-02-14 Fri>
* {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real
Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com>
Added: <2020-02-13 Thu>
* [RFC 0/9] Add an interVM memory sharing device
Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com>
Added: <2020-02-05 Wed>
* [PATCH v2 0/7] configure: Improve PIE and other linkage
Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org>
Added: <2020-01-06 Mon>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
- Got confused by QEMU aborting in the PMU code on a GICv3-only host,
which turns out to be because our error handling for "no GICv2
support" was broken. Sent a patch.
- Another push towards getting texi-to-rST conversion done:
+ Converted a few more simple texi doc files to rST
+ Took up a patchset Paolo did for more automated conversion, and
sorted out the parts it didn't deal with, to get it to a point
where it could delete almost all of the texinfo sources. Sent
a big patchset to the list for review.
- patch review:
+ Gumstix cleanup patchset
+ rth's series to honour more HCR_EL2 traps
+ add a few missing devices to integratorcp
+ get the number of implemented priority bits in GICv2 right
* VIRT-241 [QEMU ISA Support for A-profile]
- Implemented the v8.3-RCPC, v8.4-RCPC and v8.3-CCIDX extensions,
and sent patches to the list
thanks
-- PMM
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: posted updated v5
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m. Fix
committed to trunk and backported to gcc-9
* GCC upstream validation:
- reported a couple of failures/regressions
- working on reproducing a non-functional code problem with spec2006
on arm with LTO and -Os
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* spec2006 / LTO / Os / aarch32
* FDPIC GDB
Four day week.
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Lots of work here.
Noticed that our TBI handling is wrong for system mode, such that the FAR_ELx
register gets the wrong contents. Noticed that SVE isn't handling TBI at all,
much less being prepared for MTE. Noticed that even AdvSIMD would not quite
produce the correct results for LD*/ST* (multiple structures).
Rearranging the actual MTE check from the ground up. Found an odd case with
DC_ZVA that threw a wrench into that planning.
[VIRT-327 # Richard's upstream QEMU work ]
Honor more HCR_EL2 trap bits.
HPPA patch queue flushed.
Patch review for ppc "hardfloat" patch.
Patch review for memory_region_allocate_system_memory.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
- Sent out a patchset creating a 'tools' manual and moving some
docs into it that were previously in the 'interop' manual
- more code review this week than last week
- pushed out another arm pullreq
* VIRT-241 [QEMU ISA Support for A-profile]
- several patches implementing features landed in master,
so I was able to close out some of the subtasks here
thanks
-- PMM
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: handling feedback received
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m. All new
failures reported with cortex-m0 + -mpure-code are to be expected
(mainly testcases forcing options incompatible with -mpure-code)
* GCC upstream validation:
- reported a couple of failures/regressions
- looked at a problem with LTO profiled bootstrap failing on aarch32
with gcc-8. Could not reproduce with current trunk
- working on reproducing a non-functional code problem with spec2006
on arm with LTO and -Os
* misc:
- infra fixes / troubleshooting / reviews
- looked at a problem reported about addr2line and kernel symbols.
Needs more analysis
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
* spec2006 / LTO / Os / aarch32
* FDPIC GDB
== Progress ==
* More Morello (updating for new capability encoding)
* Tiny amount of GlobalISel arm32 maintenance (not committed yet)
== Plan ==
* More Morello
Same comment applies with regards to mailing lists.
On Mon, 17 Feb 2020 at 10:16, zied guermazi <guermazi_zied(a)yahoo.com> wrote:
>
> Hi Mike, hi Matthieu,
>
> I was too rapid to press the send button, sorry for the inconvienience.
> and yes, it works. I published the source code in github (https://github.com/gzied/binutils-gdb/tree/gdb_arm_coresight) ,as well as a mail in linaro mailing list (https://lists.linaro.org/pipermail/coresight/2020-February/003676.html).
Unfortunately you didn't publish your work in "PATCH" format and as
such it can't be reviewed.
> Eventhough there is still an effort needed to stabilize it for armv7, and test it for armv8, I consider this as a breakthough that we can build on the top of it.
> I will be visiting Embedded world exhibition between 25th and 27th of February in Nuremberg, Germany. are you planning to be there too. I am looking forwards to meet you there if possible to discuss possibilities of further development and integration in the main stream.
I won't be in Nuremberg next week and I'm pretty sure Mike won't be
there either. Other people on the lists might be around and
interested in meeting with you. Mike and I will be attending Linaro
Connect in Budapest between the 23rd and 27th of March. The Linaro
toolchain group will also be there so it might be the perfect
opportunity to sit down for an hour or so and have a chat.
A good day to you,
Mathieu
>
> Kind Regards
> Zied Guermazi
>
>
>
>
>
> On Monday, February 17, 2020, 06:08:26 PM GMT+1, zied guermazi <guermazi_zied(a)yahoo.com> wrote:
>
>
> Hi Mike, hi Matthieu
> it works!
>
>
>
> On Monday, December 16, 2019, 11:20:20 PM GMT+1, zied guermazi <guermazi_zied(a)yahoo.com> wrote:
>
>
> hi Mike, hi Mathieu
> last few weeks I was able to spend some time on implementing this feature, and I want to share the status with you and get your recommendation on organizational and technical level.
> so far I was able to use perf events to configure the drivers for etm and collect the traces. the code was tested successfully on an STM32MP157A discovery kit (arm v7).
> I would like to push this on git, first for review and second for integration and creating traction . Do you think it is ok to push it in this status (feature partially achieved) ? is linaro gdb git the correct one? who is the maintainer of this part of gdb? I do not have an ARMv8 platform to test. who can support here?
>
> during the implementation few technical question raised:
> - etm tracing collection requires selecting a trace sink. and I have two alternatives: either extending the "record btrace etm" command (used to start tracing) with a sink as an argument or extending the command "set record btrace" (general configuration of tracing) with etm sink sub-command? (I have hard-coded it currently to be able to progress)
> - currently I am hardcoding the path "/sys/bus/event_source/devices/cs_etm/" as the default etm source, is this guaranteed to be unique? can we have a system with many etm sources enumerated in the sysfs.
>
> for parsing the traces I will need some configuration parameters like the content of registers ETMCR, ETMIDR, ETMCCER, ETMTRACEIDR. if my understanding of the implementation of perf is correct, it is collecting them from the sysfs files located in /sys/bus/event_source/devices/cs_etm/cpu0/mgmt/. which are global for the system. my question is what will happen if two process are requesting tracing at the same time? how to differentiate between traces going to one session from the second one? is it possible to get the parameters of a given session by some kind of ioctl request to the file descriptor we get out of sys_perf_open call?
>
> I will publish those queries in the linaro coresight and gdb forums, I wanted first to align with you especially on the organizational issues, before going to a bigger round.
>
> Thanks for your support
> Zied Guermazi
>
>
