linaro-toolchain

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by Richard Henderson

Hi guys. Due to unfortunate baggage handling, I don't have my laptop and won't be able to log in Monday. I should be back online Tuesday, all going well. r~

6 years

[ACTIVITY] 2 - 6 September 2019

by Prathamesh Kulkarni

== This Week == * GCC: (a) PR86753: Addressing upstream suggestions, quite close to completion now. (b) PR78736: Fix committed to trunk. (c) PR91272: Reworked patch. (d) Bug 5464: Does not reproduce with arm-eabi-gcc-8.3.0 == Next Week == - Continue ongoing tasks

6 years

[ACTIVITY] week ending Sep. 8 2019

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= [VIRT-252] https://projects.linaro.org/browse/VIRT-252 [VIRT-280] https://projects.linaro.org/browse/VIRT-280 QEMU plugin support ([VIRT-280]) - posted {PATCH v2 0/5} fixed up semihosting fixups Message-Id: <20190904112108.2341-1-alex.bennee(a)linaro.org> - posted {PATCH v3 0/4} semihosting fixes Message-Id: <20190906124706.19145-1-alex.bennee(a)linaro.org> - more re-base of [v5 branch] - Mostly churn from MemOp changes - posted {PATCH v4 0/4} semihosting at translate time fixes Message-Id: <20190906202636.28642-1-alex.bennee(a)linaro.org> [VIRT-280] https://projects.linaro.org/browse/VIRT-280 [v5 branch] https://github.com/stsquad/qemu/tree/plugins/plugins-v5 Upstream Work ([VIRT-109]) ========================== - spent some time getting qemu-test onto 5.2.x - posted {PULL 00/12} fixes for gdbstub, gitdm and testing Message-Id: <20190902102122.1128-1-alex.bennee(a)linaro.org> - posted {PATCH v1 00/42} current testing/next queue (podman, docker, ci) Message-Id: <20190904203013.9028-1-alex.bennee(a)linaro.org> [VIRT-109] https://projects.linaro.org/browse/VIRT-109 Other Activities ================ - Connect travel administrative stuff Completed Reviews [1/1] ======================= {Qemu-arm} {PATCH v5 00/17} target/arm: Reduce overhead of cpu_get_tb_cpu_state Message-Id: <20190820210720.18976-18-richard.henderson(a)linaro.org> Absences ======== - Connect Sep 23-27th Current Review Queue ==================== * {Qemu-arm} {PATCH v2 0/5} Support disabling TCG on ARM (part 2) Message-Id: <20190903114729.3400-1-philmd(a)redhat.com> * {Qemu-devel} {PATCH v6 0/6} Allow Valgrind checking all QEMU processes Message-Id: <1566834628-485525-1-git-send-email-andrey.shinkevich(a)virtuozzo.com> * {Qemu-devel} {PATCH 0/6} exec: Cleanup watchpoints Message-Id: <20190824213451.31118-1-richard.henderson(a)linaro.org> * {PATCH 0/4} docs: add docs about use of automatic cleanup functions Message-Id: <20190823163931.7442-1-berrange(a)redhat.com> * {PATCH 0/4} docker: Update Travis-CI image to run acceptance tests Message-Id: <20190818231827.27573-1-philmd(a)redhat.com> * {PATCH v3 00/34} target/arm: Implement ARMv8.1-VHE Message-Id: <20190803184800.8221-1-richard.henderson(a)linaro.org> -- Alex Bennée

6 years

[ACTIVITY] report week ending 6 Sep

by Peter Maydell

Progress: + usual upstream maintainership stuff + notably, finished review of RTH's decodetree conversion patchset, got it into master + started on implementing semihosting v2 API (the most interesting new feature of which is support for AArch32 binaries exiting with a specified exit status) thanks -- PMM

6 years

[ACTIVITY] 2-6 Sept 2019

by Christophe Lyon

== Progress == * GCC: - FDPIC: almost OK. Found minor issues with testcases * GCC upstream validation: - reported a couple of issues. Helped with testing. - getting ready to add cortex-m33 validation with qemu * Binutils: - Non-contiguous memory regions support in the BFD linker: not started yet. * misc: - infra fixes / troubleshooting / reviews - a bit of Jira == Next == GCC: - commit FDPIC patches after final validation - binutils/linker support for non-contiguous memory regions - GCC upstream validation: Add a config for cortex-m33 (v8-m)

6 years

[ACTIVITY] Week ending 6th September 2019

by Peter Smith

[LLVM-579] Implement -fix-cortex-a8 in LLD. - Spent the week writing tests, fixing problems and polishing up the patch. Now sent upstream as D67284

6 years

[ACTIVITY] 2 - 6 September 2019

by Diana Picus

== Progress == * Investigate running benchmarks in containers [TCWG-1513] - Addressed review comments, merged changes to dockerfiles - Fixed mcf on AArch64; also managed to run on armv7 but with some failures * SVE IR fuzzer [LLVM-586] - Didn't get to work much on it, but rebuilt it with debug info * Uploaded LLVM 9.0.0-rc3 == Plan == * Investigate armv7 failures in docker * Iterate on benchmarking patches * Figure out why the fuzzer almost never introduces new code * 2 vacation days left this month

6 years

[ACTIVITY] week ending 1 Sep 2019

by Richard Henderson

[VIRT-327 # Richard's upstream QEMU work ] Fix two ppc fp launchpad bugs. Resurect patches for openrisc v1.3 Once-over review of risc-v vector extension. Posted v3 of a32 coversion to decodetree. Started poking at neon conversion to decodetree, as a prerequisite to a32 support for fp16. Some cleanups to watchpoints. Generic stuff now queued to tcg-next. DavidH is taking care of target/s390x updates, but there are some changes wanted within target/arm SVE code. r~

6 years

[ACTIVITY] 26-30 August 2019

by Christophe Lyon

== Progress == * GCC: - FDPIC: sent updated patches, already got feedback on them. almost OK * GCC upstream validation: - reported a couple of issues. Helped with testing. - getting ready to add cortex-m33 validation with qemu * Binutils: - Non-contiguous memory regions support in the BFD linker: not started yet. * misc: - infra fixes / troubleshooting / reviews - a bit of Jira == Next == GCC: - handle feedback on FDPIC patches - binutils/linker support for non-contiguous memory regions - GNU-583 - GCC upstream validation: Add a config for cortex-m33 (v8-m)

6 years

ARM GCC 8.x Performance Dropping Compared to Linaro GCC 7.x

by Yupeng Chang

Hi Dear Linaro Team, I recently found a very strange issue regarding the code performance. I have a loop written in GCC NEON. The binary of this coded generated by Linaro GCC 7.x is much faster than it generated by ARM GCC 8.x My CPU is ARM Cortex-A53 AARCH64. The compile option is: -Wall -O3 -mcpu=cortex-a53+crypto the code is like below: for (uint32 c = 0; c < channels; c += 16, roi_result += 16) { int32x4_t S1, S2, S3, S4; int16x4_t DT; DT = vld1_s16(feature1 + c + 0); S1 = vmull_lane_s16(DT, SZ, 0); DT = vld1_s16(feature1 + c + 4); S2 = vmull_lane_s16(DT, SZ, 0); DT = vld1_s16(feature1 + c + 8); S3 = vmull_lane_s16(DT, SZ, 0); DT = vld1_s16(feature1 + c + 12); S4 = vmull_lane_s16(DT, SZ, 0); DT = vld1_s16(feature2 + c + 0); S1 = vmlal_lane_s16(S1, DT, SZ, 1); DT = vld1_s16(feature2 + c + 4); S2 = vmlal_lane_s16(S2, DT, SZ, 1); DT = vld1_s16(feature2 + c + 8); S3 = vmlal_lane_s16(S3, DT, SZ, 1); DT = vld1_s16(feature2 + c + 12); S4 = vmlal_lane_s16(S4, DT, SZ, 1); DT = vld1_s16(feature3 + c + 0); S1 = vmlal_lane_s16(S1, DT, SZ, 2); DT = vld1_s16(feature3 + c + 4); S2 = vmlal_lane_s16(S2, DT, SZ, 2); DT = vld1_s16(feature3 + c + 8); S3 = vmlal_lane_s16(S3, DT, SZ, 2); DT = vld1_s16(feature3 + c + 12); S4 = vmlal_lane_s16(S4, DT, SZ, 2); DT = vld1_s16(feature4 + c + 0); S1 = vmlal_lane_s16(S1, DT, SZ, 3); DT = vld1_s16(feature4 + c + 4); S2 = vmlal_lane_s16(S2, DT, SZ, 3); DT = vld1_s16(feature4 + c + 8); S3 = vmlal_lane_s16(S3, DT, SZ, 3); DT = vld1_s16(feature4 + c + 12); S4 = vmlal_lane_s16(S4, DT, SZ, 3); DT = vrshrn_n_s32(S1, Q_VALUE); vst1_s16(roi_result + 0, DT); DT = vrshrn_n_s32(S2, Q_VALUE); vst1_s16(roi_result + 4, DT); DT = vrshrn_n_s32(S3, Q_VALUE); vst1_s16(roi_result + 8, DT); DT = vrshrn_n_s32(S4, Q_VALUE); vst1_s16(roi_result + 12, DT); } Code generated by GCC7: 294: 6b10031f cmp w24, w16 298: fc606959 ldr d25, [x10, x0] 29c: fc686922 ldr d2, [x9, x8] 2a0: fc676921 ldr d1, [x9, x7] 2a4: fc666920 ldr d0, [x9, x6] 2a8: fc686958 ldr d24, [x10, x8] 2ac: fc676957 ldr d23, [x10, x7] 2b0: fc666956 ldr d22, [x10, x6] 2b4: fc606855 ldr d21, [x2, x0] 2b8: fc686854 ldr d20, [x2, x8] 2bc: fc676853 ldr d19, [x2, x7] 2c0: fc666852 ldr d18, [x2, x6] 2c4: fc606891 ldr d17, [x4, x0] 2c8: fc686890 ldr d16, [x4, x8] 2cc: fc676887 ldr d7, [x4, x7] 2d0: fc666885 ldr d5, [x4, x6] 2d4: 0f44a063 smull v3.4s, v3.4h, v4.h[0] 2d8: 0f44a042 smull v2.4s, v2.4h, v4.h[0] 2dc: 0f44a021 smull v1.4s, v1.4h, v4.h[0] 2e0: 0f44a000 smull v0.4s, v0.4h, v4.h[0] 2e4: 0f542323 smlal v3.4s, v25.4h, v4.h[1] 2e8: 0f542302 smlal v2.4s, v24.4h, v4.h[1] 2ec: 0f5422e1 smlal v1.4s, v23.4h, v4.h[1] 2f0: 0f5422c0 smlal v0.4s, v22.4h, v4.h[1] 2f4: 0f6422a3 smlal v3.4s, v21.4h, v4.h[2] 2f8: 0f642282 smlal v2.4s, v20.4h, v4.h[2] 2fc: 0f642261 smlal v1.4s, v19.4h, v4.h[2] 300: 0f642240 smlal v0.4s, v18.4h, v4.h[2] 304: 0f742223 smlal v3.4s, v17.4h, v4.h[3] 308: 0f742202 smlal v2.4s, v16.4h, v4.h[3] 30c: 0f7420e1 smlal v1.4s, v7.4h, v4.h[3] 310: 0f7420a0 smlal v0.4s, v5.4h, v4.h[3] 314: 0f138c63 rshrn v3.4h, v3.4s, #13 318: 0f138c42 rshrn v2.4h, v2.4s, #13 31c: 0f138c21 rshrn v1.4h, v1.4s, #13 320: 0f138c00 rshrn v0.4h, v0.4s, #13 324: 6d3e0a63 stp d3, d2, [x19, #-32] 328: 6d3f0261 stp d1, d0, [x19, #-16] Code generated by GCC8: 26c: 6b0b02ff cmp w23, w11 270: fc606922 ldr d2, [x9, x0] 274: fc666941 ldr d1, [x10, x6] 278: fc666920 ldr d0, [x9, x6] 27c: 0f44a000 smull v0.4s, v0.4h, v4.h[0] 280: 0f542020 smlal v0.4s, v1.4h, v4.h[1] 284: fc6668e1 ldr d1, [x7, x6] 288: 0f642020 smlal v0.4s, v1.4h, v4.h[2] 28c: fc646945 ldr d5, [x10, x4] 290: fc666901 ldr d1, [x8, x6] 294: 0f742020 smlal v0.4s, v1.4h, v4.h[3] 298: fc646921 ldr d1, [x9, x4] 29c: 0f44a021 smull v1.4s, v1.4h, v4.h[0] 2a0: 0f5420a1 smlal v1.4s, v5.4h, v4.h[1] 2a4: fc626945 ldr d5, [x10, x2] 2a8: 0f138c03 rshrn v3.4h, v0.4s, #13 2ac: fc626920 ldr d0, [x9, x2] 2b0: 0f44a000 smull v0.4s, v0.4h, v4.h[0] 2b4: 0f5420a0 smlal v0.4s, v5.4h, v4.h[1] 2b8: fc606945 ldr d5, [x10, x0] 2bc: 0f44a042 smull v2.4s, v2.4h, v4.h[0] 2c0: 0f5420a2 smlal v2.4s, v5.4h, v4.h[1] 2c4: fc6468e5 ldr d5, [x7, x4] 2c8: 0f6420a1 smlal v1.4s, v5.4h, v4.h[2] 2cc: fc6268e5 ldr d5, [x7, x2] 2d0: 0f6420a0 smlal v0.4s, v5.4h, v4.h[2] 2d4: fc6068e5 ldr d5, [x7, x0] 2d8: 0f6420a2 smlal v2.4s, v5.4h, v4.h[2] 2dc: fc646905 ldr d5, [x8, x4] 2e0: 0f7420a1 smlal v1.4s, v5.4h, v4.h[3] 2e4: fc626905 ldr d5, [x8, x2] 2e8: 0f138c21 rshrn v1.4h, v1.4s, #13 2ec: 0f7420a0 smlal v0.4s, v5.4h, v4.h[3] 2f0: 0f138c00 rshrn v0.4h, v0.4s, #13 2f4: fc606905 ldr d5, [x8, x0] 2f8: 0f7420a2 smlal v2.4s, v5.4h, v4.h[3] 2fc: 0f138c42 rshrn v2.4h, v2.4s, #13 300: 6d000e62 stp d2, d3, [x19] 304: 6d010261 stp d1, d0, [x19, #16] 308: 91008273 add x19, x19, #0x20 I did some tests on different compile options, and found that option "-fschedule-insns" on GCC 7 will generate code that runs faster, if I disable schedule-insns, GCC7 will generate the same code as GCC8. However, this option seems don't work on GCC8, if I enable "-fschedule-insns" with GCC8, the code generated by GCC8 is even slower. If I disable "-fschedule-insns" with GCC8, the generated code is just like the sequence as in C code. I compiled my code with -O3, which means -fschedule-insns will be enabled by default. With this option enabled, GCC7 will reschedule instructions, and it seems that GCC7 will arrange the same instructions all together, but GCC8 doesn't do that, or GCC8 will reschedule instructions in a worse way. My question is, is this behavior expected in GCC8, GCC9 and the future version? Is this change in GCC code scheduling related to the fix of "spectre and mitigation" ? If I want the same instruction scheduling mechanism in GCC8, what can I do ? Thank you for looking into this. Looking forward to your reply! Tomas Chang Aug 19, 2019

6 years

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