o LLVM
* Back to machine outliner after vacation
- Rebased on upstream master branch
- Working on stack alignment and refactoring.
o Misc
* Preparing BKK19 and EuroLLVM trips.
* Various meetings and discussions.
* PR88838
- I have a patch which solves this.
* adds iv in Pmode but compare_type in 32bit
- It exposes a latent bug in fwprop in regression testing
- Looking into it
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
Progress:
[VIRT-274 # ARMv8.2-FHM, Floating-point multiplication variant ]
Now upstream.
[VIRT-298 # ARMv8.4-CondM, Condition flag manipulation ]
[VIRT-329 # ARMv8.5-CondM, Condition flag manipulation ]
[VIRT-337 # ARMv8.0-SB, Speculation Barrier ]
[VIRT-338 # ARMv8.0-PredInv, Prediction Invalidation ]
[VIRT-330 # ARMv8.5-FRINT, Floating-point to integer ]
Posted an omnibus of SB+PredInv+CondM+FRINT that I have
labeled "v3", as 3 > any individual revision previously used.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed s390x vector patch set v2.
Implemented pattern groups in decodetree.
Prototyped A32 conversion to decodetree;
started a second revision that incorporates T32.
Started looking at
https://bugs.linaro.org/show_bug.cgi?id=4274
I can swizzle things around by changing the group name from
"cp_regs" to the predefined "system", but somehow those regs
are *also* registered with "general". Which means the
undesired behaviour by which "info regs" prints all of the
system registers still exists.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ upstream code review and pull request handling
+ respin of patchset to enable building our Sphinx RST documentation
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ progress on M-profile floating point:
- have written code to handle the smaller parts of the feature
(insn decode, registers, etc)
- started on changes to exception handling
- lazy save/restore still to do after that
* a lot of admin/meeting stuff this week
* softfreeze now less than two weeks away, need to
focus on what needs to be done before then...
thanks
-- PMM
[LLVM-494] LLD is now turned on for clang linux kernel defconfig builds
[LLVM-542] Worked out how to get Zephyr (Linaro's choice of IoT
embedded OS) compiling with clang. Looks like it is going to be
difficult to get linking with clang/lld so I've used the gcc/ld.bfd
for now.
Linux kernel sent a draft patch to try and alleviate some object
ordering problems that arise when linking the linux kernel with LTO.
[Misc]
Intel patch to add CET to LLD https://reviews.llvm.org/D58102
I mention this as this is related to BTI and CFI and
.note.gnu.property sections. There has been some pushback to the use
of .note.gnu.property sections, and in Intel's case their 2 level PLT
scheme although it seems like as this has been mitigated by the
presence of this option in gcc for some time. I have noticed that we
tend to do design of a feature in one community (LLVM, GNU) and then
attempt to win over the other one with leverage that the other
community supports it. We may need to cast our early feedback net a
bit wider to mitigate the chance that one of the communities blocks
one of our features.
There was an interesting RFC on a linker feature for improving
code-size for mobile phones
http://lists.llvm.org/pipermail/llvm-dev/2019-February/130583.html in
essence an application is developed with loadable features implemented
in DSOs loaded by dlopen. The entry points of the DSO are recorded,
then all the input objects are given to the static linker which then
performs LTO and creates stripped down DSOs that must be loaded at a
specific offset from the application (shrinking them but losing the
shared part of DSO).
QEMU Tooling ([VIRT-252])
=========================
QEMU plugin support ([VIRT-280])
- posted {PATCH v3 0/3} softmmu demacro Message-Id:
<20190215143115.28777-1-alex.bennee(a)linaro.org>
- looks like there is still a bug on x86 TCG Message-Id:
<20190219182528.GA19925@flamenco>
- started v4 re-base, but realised we need better testing so
- posted {PATCH v2 00/16} Enabling tcg/tests for cris and system
mode xtensa & arm Message-Id:
<c3a65d4b-8720-2957-1394-032823a78760(a)redhat.com>
- started writing an i386 test case (x86 exercises more of the
softmmu edge cases)
- started reviewing v3 of plugin patches
[VIRT-280] https://projects.linaro.org/browse/VIRT-280
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v5} hw/block: better reporting on pflash backing file
mismatch Message-Id: <20190227111347.15063-1-alex.bennee(a)linaro.org>
- tested the possible ahci/migrate fix Message-Id:
<20190227121052.GD2602@work-vm> for hang identified last week
- posted {PULL 0/7} softfloat updates, mostly for s390x Message-Id:
<20190226141201.16999-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 0/6} current state of gitdm/next Message-Id:
<20190226164656.mhasc4xxfjf34hns@function>
- and follow-up {PATCH v2 0/5} gitdm/next updates Message-Id:
<20190301100310.22345-4-alex.bennee(a)linaro.org>
- added some stats to VIRT-26/VIRT-326 for possible KPI use
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
Other
=====
- more drafting of Connect talk
Completed Reviews [1/1]
=======================
{PATCH v2 00/11} pflash: Fixes and cleanups
Message-Id: <20190226193408.23862-5-armbru(a)redhat.com>
- CLOSING NOTE [2019-03-01 Fri 16:59]
Looks like a good cleanup
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {RFC v2 00/38} Plugin support
Message-Id: <20181209193749.12277-1-cota(a)braap.org>
* {Qemu-devel} {PATCH 00/23} tests/tcg/xtensa: conditionalize xtensa tests
Message-Id: <20190219061111.10231-1-jcmvbkbc(a)gmail.com>
* {PATCH 00/10} Rework debug exception handling code
Message-Id: <20190301132809.24653-7-will.deacon(a)arm.com>
* {PATCH v2 00/11} Enable build and install of our rST docs
Message-Id: <20190228145624.24885-1-peter.maydell(a)linaro.org>
* {PATCH+RFC 0/6} target/arm: Define cortex-a{73,75,76}
Message-Id: <20190223023957.18865-1-richard.henderson(a)linaro.org>
* {PATCH v3 00/20} Acceptance Tests: target architecture support
Message-Id: <20190221005753.27955-1-crosa(a)redhat.com>
--
Alex Bennée
== Progress ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
- Committed upstream
* [Thumb GlobalISel] Support G_CTLZ [LLVM-543]
- Committed upstream
- We now have the same level of support for Thumb2 and ARM mode
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Tested and uploaded rc3
== Plan ==
* Out of office between 4 - 8 March (i.e. next week)
* GlobalISel bugfixing and cleanup (both ARM and Thumb2)
== Progress ==
* PR88836
- I have a patch (for backend and CSE) which now passes bootstrap and
regression except for one testcase failure (which looks like a pattern
issue). Looking into it.
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
- Not convinced that it is a gcc issue. Looking into the dwarf specification.
* PR88838
- Looking at it.
- Also familiarising with auto-vectorisation of SVE
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
