== Progress ==
* GCC
- FDPIC patch series: received a bit of feedback. Noticed problems
with v8m and libssp, should be easy to fix
- Started rebasing uclibc patches on top of uclibc-ng
* GCC upstream validation:
- reported a few failures/regressions
- looking at some random noise in testing
* Infrastructure:
- patch reviews
- cleanup/improvements
* misc (conf-calls, meetings, emails, ....)
== Next ==
* FDPIC: uclibc
* GCC upstream validation
* Training Mon/Tue
== Progress ==
o GNU release transition
* 6.4 and 7.3 2018.05 RC1 deployed
o LLVM
* Thumbv8 bot failures [TCWG-1400]:
- Testing fix on arm, armhf, armv7 and armv8.
o Misc
* Various meetings and discussions.
== This Week ==
* TCWG-1234: Code hoisting and register pressure (8/10)
- Created patches for restricting hoisting out of blocks on loop exit
but that was false alarm.
- Investigating interaction of forwprop, code hoisting and register pressure.
- Started upstream discussion.
* GCC bugs (1/10)
- TCWG-125: static_cast not working on ARM hardfp: Asked upstream on
libvolk list for help to reproduce.
- PR85787: Created patch, investigating regressions caused due to it.
* Misc (1/10)
- Meetings
== Next Week ==
- TCWG-1234
- GCC bugs
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ sent patch for minor bug where FRECPX was not honouring FPCR.FZ
+ looking at migration failure for TCG VMs using Secure mode. I know
what the bug is, but need to figure out how to fix it without breaking
migration compatibility for TCG VMs which don't use Secure mode...
+ various miscellaneous minor bug fixing and code review
* VIRT-164 [improve Cortex-M emulation]
+ MPC emulation:
- sent out first version of patchset that implements the required
IOMMU core code features and the MPC device that uses them; fielded
various code review discussions on it
thanks
-- PMM
Half of the week spent investigating identical code folding -icf=safe.
Turns out that upstream have a proposal that is much further along so
shifted focus on to doing as much as I can to help it along.
Found out that for some use cases of AArch64 PIC the small code model
is inappropriate as the code segments may not be 4k aligned. Started
looking into what it would take to implement the tiny code model in
LLVM (supports only small and large at the moment). Built a small
prototype to handle the easiest absolute addressing case, much more
work needed to handle PIC and TLS.
Not a lot of tangible progress, but I think I have learned a bit more
about LLVM.
Planned Absences
- Friday 25th May (holiday).
- Monday 28th May (UK public holiday)
Hello,
I just noticed that the manifest file of the Linaro gcc-5.5-2017.10 release under http://releases.linaro.org/components/toolchain/gcc-linaro/5.5-2017.10/x86_… from January, 13th 2018 differs from the original version from October 2017: the binutils, gdb and abe versions are different.
Could you please tell me the reason for the changes?
Thank you very much!
Andrej Gantvorg