NB Last _6_ working days.
Centralised benchmark source - TCWG-354 [6/10]
* Abe integration
* Wrote up some notes on collaborate
* Enabled clang build, which flushed out some bugs, now fixed
* LAVA reporting script
Port to microinstance - TCWG-432 [1/10]
* Investigating issues with Juno boot
** One turns out to be user error
** The other is a failed heath check, passed to the admins
Backport benchmarking - TCWG-352 [2/10]
* Difficulties with passing information from matrix children to parent
** Came up with an ugly workaround, may have thought of a better one
Misc [3/10]
=Plan=
Holidays until 4th January
# Progress #
* TCWG-156, GDB Test-Suite Parity Between Aarch64 and x86_64. Done. [4/10]
After two patches are committed, except some tests written for x86_64
unnecessarily, the test results between aarch64 and x86_64 looks no
difference.
* TCWG-424, timeout when interrupt the inferior in remote debugging. [3/10]
The fail is caused by different two problems. Two patches are ready,
and being regression tested.
* TCWG-171, Enable gdb core file tests when testing remotely. [1/10]
Write down my conclusion as it can't be fixed.
* Upstream review, [2/10]
** Review patch about handling ada aarch64 HVA array in GDB.
** Discuss target description of GDB for cortex-m device with openocd.
# Plan #
* Post patches upstream for TCWG-424,
* Patches review.
* On holiday since Wed.
--
Yao
Hi All,
I am interested in understanding Linaro LLVM activity.
I have already gone through
https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM.
Could you please guide me on below questions.
1. On which LLVM & clang version, linaro is actively working now ?
2. Where can I find the latest "linaro-llvm" source code & binary? I could
not find any official git repo for "linaro-llvm" at https://git.linaro.org/.
3. Could you please explain Linaro LLVM working model? How
similar/different it is when compared with Linaro-GCC engagement.
4. Certain links (e.g Roadmap) at
https://wiki.linaro.org/WorkingGroups/ToolChain/LLVM ask for login
credentials. Any comment on how to obtain the permission?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
* 1 day off (Friday) (2/10)
== Progress ==
* Validation: (2/10)
- improvements to the comparison scripts
- updated ABE stable and staging branches
* GCC: (3/10)
- TCWG-484: sent a new version of the patch to address problems with
the testsuite and target attributes.
- TCWG-485/PR68620: WIP, trying to understand the regressions
introduced by my patch
* Misc (conf calls, meetings, emails, ...) (3/10)
== Next ==
Holidays until next year
Hi All,
As per release notes, linaro_binutils-2_25-2015_01-2_release should be
present at http://git.linaro.org/toolchain/binutils-gdb.git.
But I am not able to see any "linaro_binutils" tags on
https://git.linaro.org/toolchain/binutils-gdb.git/tags.
Am I doing any mistake? or on git it is renamed to something else (same as
FSF binutils tags?).
Apology for asking such a trivial question.
Thanks for your time.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2015.12 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn231642 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2015.11
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2015.12/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn231642
* Backport of [Bugfix] [AArch32] 1/4 PR63870 Add qualifiers for NEON builtins
* Backport of [Bugfix] [AArch32] 2/4 PR63870 Mark lane indices of
vldN/vstN with appropriate qualifier
* Backport of [Bugfix] [AArch32] 3/4 PR63870 Remove error for invalid
lane numbers
* Backport of [Bugfix] [AArch32] 4/4 PR63870 Remove xfails for ARM targets
* Backport of [Bugfix] [AArch32] PR67305, tighten
neon_vector_mem_operand on eliminable registers
* Backport of [Bugfix] [AArch32] remove unused variable
* Backport of [Bugfix] [AArch64] PR 63304 Fix issue with global state
* Backport of [Bugfix] [AArch64] PR63304 Handle literal pools for
functions > 1 MiB in size
* Backport of [Bugfix] [AArch64] PR 68088: Fix RTL checking ICE due to
subregs inside accumulator forwarding check
* Backport of [Bugfix] [AArch64] PR rtl-optimization/67218
* Backport of [Bugfix] PR 56036 fix typo in doc
* Backport of [Bugfix] PR rtl-optimization/68236: Exit early from
autoprefetcher lookahead if not in haifa sched
* Backport of [Bugfix] PR tree-optimization/68234 Improve range info
for loop Phi node
* Backport of [AArch32] 1/4 Change GET_MODE_INNER to always return a
non-void mode
* Backport of [AArch32] 2/3 Make if_neg_move and if_move_neg into insn_and_split
* Backport of [AArch32] 2/4 Control the FMA steering pass in tuning
structures rather than as core property
* Backport of [AArch32] 3/3 Expand mod by power of 2
* Backport of [AArch32] 3/4 Replace the pattern GET_MODE_BITSIZE
(GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m)
* Backport of [AArch32] 4/4 Fix - Introduce new inline functions for
GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION
* Backport of [AArch32] 4/4 Introduce new inline functions for
GET_MODE_UNIT_SIZE and GET_MODE_UNIT_PRECISION
* Backport of [AArch32/AArch64] 2/2 Add a new Cortex-A53 scheduling model
* Backport of [AArch32] Add missing v8a cpus to the t-aprofile file
* Backport of [AArch32] Fix checking RTL error in cortex_a9_sched_adjust_cost
* Backport of [AArch32] Fix for testcase after r228661
* Backport of [AArch32] Initialise cost to COSTS_N_INSNS (1) and
increment in arm rtx costs
* Backport of [AArch32] libgcc: include crtfastmath
* Backport of [AArch32] Unified assembler in ARM state
* Backport of [AArch64] 1/2 Give AArch64 ROR (Immediate) a new type attribute
* Backport of [AArch64] 1/2 Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G
* Backport of [AArch64] 1/2 Rename test source file for reuse
* Backport of [AArch64] 1/3 Add the option -mtls-size
* Backport of [AArch64] 1/3 Expand signed mod by power of 2 using CSNEG
* Backport of [AArch64] 2/2 Implement -fpic for -mcmodel=small
* Backport of [AArch64] 2/2 Implement TLS IE for tiny model
* Backport of [AArch64] 2/3 Rename SYMBOL_TLSLE to SYMBOL_TLSLE24
* Backport of [AArch64] 3/3 Implement local executable mode for all memory model
* Backport of [AArch64] Add initial qualcomm support
* Backport of [AArch64] Add missing entries in iterator vwcore
* Backport of [AArch64] Cleanup whitespace in aarch64.c
* Backport of [AArch64] Cortex-A57 Choose some new branch costs
* Backport of [AArch64] Define TARGET_UNSPEC_MAY_TRAP_P
* Backport of [AArch64] Distinct costs for sign and zero extension
* Backport of [AArch64] Do not ICE after apologising for -mcmodel=large -fPIC
* Backport of [AArch64] Don't allow -mgeneral-regs-only to change the
.arch assembler directives
* Backport of [AArch64] Don't transform sign and zero extends inside mults
* Backport of [AArch64] Fall back to -fPIC if no support of -fpic in binutils
* Backport of [AArch64] Fix for branch offsets over 1 MiB
* Backport of [AArch64] Fix ICE on (const_double:HF 0.0)
* Backport of [AArch64] Fix insn types
* Backport of [AArch64] Fix output assembly bug under TLSIE ILP32
* Backport of [AArch64] Handle vector float modes properly in
aarch64_output_simd_mov_immediate
* Backport of [AArch64] Mark GOT related MEM rtx as const to help RTL loop IV
* Backport of [AArch64] Properly handle simple arith+extend ops in rtx costs
* Backport of [AArch64] Rename SYMBOL_SMALL_GOTTPREL to SYMBOL_SMALL_TLSIE
* Backport of [AArch64] Restrict pic-small.c by new test directive
* Backport of [AArch64] Tighten direct call pattern for sibcall to
repair -fno-plt
* Backport of [AArch64] Tighten direct call pattern to repair -fno-plt
* Backport of [Testsuite] [AArch32] Fix thumb2-slow-flash-data.c failures
* Backport of [Testsuite] [AArch32] Switch ARM to unified asm
* Backport of [Testsuite] [AArch64] Add more TLS local executable testcases
* Backport of [Testsuite] [AArch64] Check branch types for noplt testcases
* Backport of [Testsuite] [AArch64] Fix gcc.target/aarch64/vclz.c
* Backport of [Testsuite] [AArch64] Fix some target attribute inlining
tests for -fPIC
* Backport of [Testsuite] [AArch64] Restrict got_mem_hoist_1.c with
small memory model
* Backport of [Testsuite] [AArch64] Skip tiny and large code model on
gcc.target/aarch64/pic-small.c
* Backport of [Testsuite] Add --param
sra-max-scalarization-size-Ospeed to sra-12.c
* Backport of [Testsuite] Fix target selector in
gcc.target/i386/noplt-[1234].c testcases
* Backport of [Misc] Allow sibcalls in no-PLT PIC
* Backport of [Misc] Eliminate PLT stubs for specified external
functions via -fno-plt
* Backport of [Misc] Fix for ICE with -g on testcase with incomplete types
* Backport of [Misc] Fix memory leak and wrong invariant dependence
computation in IVOPT
* Backport of [Misc] Improve rtl loop inv cost by checking if the inv
can be propagated to address uses
* Backport of [Cleanup] [AArch32/AArch64] fix ChangeLog
* Backport of [cleanup] [AArch32] Remove uses of CONST_DOUBLE_HIGH/LOW
* Backport of [Cleanup] [AArch64] Delete aarch64_symbol_context which
is not used
* Backport of [cleanup] [AArch64] Move iterators from atomics.md to iterators.md
* Backport of [cleanup] [AArch64] Remove uses of CONST_DOUBLE_HIGH,
CONST_DOUBLE_LOW
* Backport of [Doc] [AArch64] Document several AArch64-specific test directives
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Centralised benchmark source - TCWG-354 [6/10]
* Understood CoremarkPro run rules/behaviour better
* Experimented with shortening runs while still giving meaningful results
* Cleaned up build/run scaffolding
Port to microinstance - TCWG-432 [1/10]
* Got access to microinstance, learned a bit about SSL in the process
Backport benchmarking - TCWG-352 [2/10]
* Fixed 'build with sysroot' code for current deliverable shape
* Fixed a problem with multiple manifests
=Plan=
Review, test, debug build-triggers-benchmark job
Finish off Coremark Pro integration
Review security with shared uinstance/main instance code
Expose more data, benchmarks to bundles
Debug/test Jenkins job in microinstance
Create bootable image for at least 1 target, or know what the problems are
Write up noise control report (if time)
More support for SPEC-on-Android?
=Absence=
Holiday 22nd December - 1st January
== This Week ==
* TCWG-72 (2/10)
- Another iteration.
* LTO (4/10)
- Building spec with different combinations of -flto -flto-partition
-flto-compression-level
- Builds cleanly on AArch64, ICE's on ARM for 447.dealII with -flto
- Looked at segfault with 483.xalanpack
* TCWG-319 benchmarking (1/10)
- fp benchmark results on:
r1-a12: -0.04 %
cortex-a53: -0.09 %
cortex-a57: -0.14%
- int benchmarks completed running for reference revision on cortex-a15
- int benchmarks with-patch runnning on cortex-a15
* TCWG-310 benchmarking (1/10)
- r1-a12: 0.11%
- Benchmark jobs failed on a53, a57.
* Misc (2/10)
- Submitted patch to fix building 450.soplex
- Looked at how to write ipa pass, ipa-pure-const and ipa-cp.
- Meetings
== Next Week ==
- tcwg-319, tcwg-310 benchmarking
- tcwg-72
- LTO
== This week ==
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (7/10)
- Implemented signed and unsigned add, subtract, and multiply
overflow standard patterns
- Investigated testing of overflow patterns
* Misc (3/10)
- Conference calls
- Misc ARM Housekeeping
- Lost connectivity due to old ARM Unix VPN Client
== Next week ==
* TCWG-317 - Exploit wide add operations when appropriate for Aarch32
- Minor code update to address upstream comment
* Vacation until rest of year
