Hi,

* continued with my attempts to vectorize Viterbi: - finished implementation of conditional store sinking in cselim pass (I did only limited testing). - reconsidered the idea of safe load if-conversion if an adjacent field of the same structure is accessed unconditionally - this may be incorrect. Instead I tried the last, not yet committed, patch by Sebastian Pop that implements if-conversion for such cases of not-safe data accesses. His patch if-converts the loop in Viterbi, however, it also makes the loop not vectorizable - additional work should be done in the data-refs analysis and the vectorizer to make it work. Sebastian is working on the first part, and I'll help him with the vectorizer part if necessary.

* analyzed EEMBC DenBench, couldn't find any action items for now. But vld/vst support of strided data accesses should be very useful for these benchmarks.

* fixed GCC PR testsuite/47057

* looking into SLP of reduction as in PR 41881. I saw similar patterns several times in DenBench, but I'm not sure that SLP of reduction is enough to vectorize all of these cases.

Happy New Year, Ira