Linaro-uefi

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811 discussions

[PATCH v2] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Futher, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 5 months

[PATCH] Platforms: add resolution for new library class 'ArmMmuLib'

by Ard Biesheuvel

Now that the page table manipulation code has been split off from ArmLib into ArmMmuLib, we need a resolution for this new library class in all platforms. For most platforms, this is simply a matter of adding a new line ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf to a common [LibraryClass] section. For D02/D03, which were users of the special PEI_CORE/PEIM implementation of ArmLib, we drop the reference to this special version from the [LibraryClasses.PEI_CORE] section (since PEI core does use ArmLib but does not use the MMU code), and replace the one in [LibraryClasses.PEIM] with the new ArmMmuPeiLib.inf implementation, which is the new version that takes care not to issue cache maintenance ops on NOR flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- This change will be needed as soon as I commit the series 'ArmPkg: refactor MMU handling routines into separate ArmMmuLib', which is good to go from review perspective. If people are ok with this patch, I will merge it at the same time as the series (unless there are other reasons to wait) Since this change is not bisectable anyway (since the EDK2 change and the OPP change both need to occur at the same time), I saw little point in splitting this into several patches. Chips/Hisilicon/Pv660/Pv660.dsc.inc | 4 ++-- Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc | 1 + Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 1 + Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc | 1 + Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc | 1 + 8 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660.dsc.inc b/Chips/Hisilicon/Pv660/Pv660.dsc.inc index 2a0ffac9c72d..029608ceeb78 100644 --- a/Chips/Hisilicon/Pv660/Pv660.dsc.inc +++ b/Chips/Hisilicon/Pv660/Pv660.dsc.inc @@ -65,6 +65,7 @@ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf # Versatile Express Specific Libraries ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf @@ -166,7 +167,6 @@ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf [LibraryClasses.common.PEIM] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf @@ -186,7 +186,7 @@ ## Fixed compile error after upgrade to 14.10 PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc index f6606cafb849..2b15d7f5667b 100644 --- a/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc +++ b/Chips/TexasInstruments/Omap35xx/Omap35xxPkg.dsc @@ -34,6 +34,7 @@ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 437286876a31..6b9446a1387d 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -101,6 +101,7 @@ DEFINE DO_KCS = 0 ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index c73bd55c1558..0f8dd814ad15 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -104,6 +104,7 @@ DEFINE DO_KCS = 1 ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 490e08eb9248..4f41fb159f19 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -34,6 +34,7 @@ !include OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress.dsc.inc [LibraryClasses.common] + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc index 9daf3c8ff512..ef8fd971e66b 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-CTA15-A7.dsc @@ -39,6 +39,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1e871b541c6e..65b14eb793a8 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -42,6 +42,7 @@ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf diff --git a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc b/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc index e24df3b7a8df..3c2b767552fa 100644 --- a/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc +++ b/Platforms/TexasInstruments/BeagleBoard/BeagleBoardPkg.dsc @@ -32,6 +32,7 @@ [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmPlatformLib|OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/BeagleBoardLib.inf ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf -- 1.9.1

8 years, 5 months

[PATCH 0/2] Platforms/ARM/Juno: tidy Acpi GTDT

by evan.lloyd＠arm.com

From: Evan Lloyd <evan.lloyd(a)arm.com> These patches make minor source updates to the Juno GTDT. There is no functional change, only source code improvements. Code available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/GTDTbis_v1 Alexei (1): Platforms/ARM/Juno: fix GTDT compilation error. Evan Lloyd (1): Platforms/ARM/Juno: ameliorate misleading GTDT name. Platforms/ARM/Juno/AcpiTables/Gtdt.aslc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

[PATCH v4 0/4] arm64, xen: add xen_boot support into grup-mkconfig

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This patchset add xen_boot support into grup-mkconfig for generating xen boot entrances automatically Also update the docs/grub.texi for new xen_boot commands. This patchset has been tested on Foudation model with a bug fix: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00205.html ChangeLog: v4: http://lists.gnu.org/archive/html/grub-devel/2016-05/ according to the XSM loading mechanism of Xen(upstreamed), update the introduction of xen_module commands in docs/grub.texi v3: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00314.html reorder the patches update the introduction of xen_module commands in docs/grub.texi v2: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00282.html add "--nounzip" option support in xen_module use "feature_xen_boot" instead of "grub_xen_boot" update the introduction of xen boot commands in docs/grub.texi v1 :first upstream patchset: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00264.html Fu Wei (4): i386,xen: Add xen_hypervisor and xen_module aliases for i386 arm64: add "--nounzip" option support in xen_module command * util/grub.d/20_linux_xen.in: Add xen_boot command support arm64: update the introduction of xen boot commands in docs/grub.texi docs/grub.texi | 33 ++++++++++----------------------- grub-core/loader/arm64/xen_boot.c | 17 +++++++++++++++++ grub-core/loader/i386/xen.c | 7 +++++++ grub-core/normal/main.c | 2 +- util/grub.d/20_linux_xen.in | 13 ++++++++++--- 5 files changed, 45 insertions(+), 27 deletions(-) -- 2.5.5

8 years, 5 months

[PATCH] Platforms/FVP: drop GICv2 support

by Ard Biesheuvel

Now that ARM Trusted Firmware has dropped support for the legacy VE memory map (which means it can only support the FVP Foundation model in GICv3 mode), and runs the GICv3 in native mode by default on the secure side (which prevents a GICv2 compatible GICv3 from being driven in v2 mode on the non-secure side), there is little point in keeping the GICv2 legacy ifdefs in the FVP dsc. So remove them. Note that we will still be able to support FVP Base in GICv2 mode after applying this patch, but running it will require a special build of ATF with FVP_GICV2 defined. Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index 1e871b541c6e..3d67823cf5db 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -82,10 +82,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE -!ifdef ARM_FVP_GICV3_WITH_V2_LEGACY - gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE -!endif - [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP" @@ -154,14 +150,9 @@ # # ARM General Interrupt Controller # -!ifdef ARM_FVP_LEGACY_GICV2_LOCATION - gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000 -!else gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 -!endif # # ARM OS Loader -- 1.9.1

8 years, 5 months

[PATCH 0/4] Convert FVP to ASLC to help build stability

by Graeme Gregory

This series requires the patch sent to edk2-devel :- EmbeddedPkg/AcpiLib: add GICC table init macro for ACPI 6.0 To enable the new macro for GICC structure in ACPI 6.0+ Thanks Graeme

8 years, 5 months

[PATCH] Platforms/FVP: Fix MADT to run the Foundation model in GICv3 mode with 4 CPUs

by Ard Biesheuvel

This upgrades the MADT table so that it exposes the GIC as a v3. The virtual base address and interrupt, and the hypervisor base address are corrected as well. Since the Foundation model has 4 cores at the most, and since refactoring this code to update the ACPI tables dynamically based on the actual core count is more trouble that its worth, remove the second cluster while we are at it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- This applies in combination with Graeme's 'Platforms/ARM: Fix FVP FADT version' Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl | 116 ++++---------------- 1 file changed, 19 insertions(+), 97 deletions(-) diff --git a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl index 9cd303184352..7d915621efef 100644 --- a/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl +++ b/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/apic.asl @@ -61,9 +61,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */ -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0 [0001] Efficiency Class : 00 @@ -82,9 +82,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000001 [0001] Efficiency Class : 00 @@ -103,9 +103,9 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000002 [0001] Efficiency Class : 00 @@ -124,103 +124,25 @@ [0004] Performance Interrupt : 00000000 [0008] Parked Address : 0000000000000000 [0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 +[0008] Virtual GIC Base Address : 000000002C02F000 +[0008] Hypervisor GIC Base Address : 000000002C010000 +[0004] Virtual GIC Interrupt : 00000019 [0008] Redistributor Base Address : 0 [0008] ARM MPIDR : 0000000000000003 [0001] Efficiency Class : 00 [0003] Reserved : 000000 -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000004 -[0004] Processor UID : 00000004 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000100 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000005 -[0004] Processor UID : 00000005 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000101 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000006 -[0004] Processor UID : 00000006 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000102 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - -[0001] Subtable Type : 0B [Generic Interrupt Controller] -[0001] Length : 50 -[0002] Reserved : 0000 -[0004] CPU Interface Number : 00000007 -[0004] Processor UID : 00000007 -[0004] Flags (decoded below) : 00000001 - Processor Enabled : 1 - Performance Interrupt Trigger Mode : 0 - Virtual GIC Interrupt Trigger Mode : 0 -[0004] Parking Protocol Version : 00000000 -[0004] Performance Interrupt : 00000000 -[0008] Parked Address : 0000000000000000 -[0008] Base Address : 000000002C000000 -[0008] Virtual GIC Base Address : 0 -[0008] Hypervisor GIC Base Address : 0 -[0004] Virtual GIC Interrupt : 0 -[0008] Redistributor Base Address : 0 -[0008] ARM MPIDR : 0000000000000103 -[0001] Efficiency Class : 00 -[0003] Reserved : 000000 - [0001] Subtable Type : 0C [Generic Interrupt Distributor] [0001] Length : 18 [0002] Reserved : 0000 [0004] Local GIC Hardware ID : 00000000 [0008] Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */ [0004] Interrupt Base : 00000000 -[0001] Version : 02 +[0001] Version : 03 [0003] Reserved : 000000 + +[0001] Subtable Type : 0E [Generic Interrupt Redistributor] +[0001] Length : 10 +[0002] Reserved : 0000 +[0008] Base Address : 000000002F100000 /* armv8 FVP Base GIC redistributor base addr */ +[0004] Region Size : 00200000 -- 2.7.4

8 years, 5 months

[PATCH 0/2] Platforms/ARM/uno: update SPCR to aslC

by evan.lloyd＠arm.com

From: Evan Lloyd <evan.lloyd(a)arm.com> This patch set comprises a split version of the single patch previously submitted under the title "Platforms/ARM: Juno: Acpi - update SPCR to aslc." The split divides the change to aslC format from the update to use PCDs. Code is available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/SPCR_v3 Original Commit message was: Amend the Serial Port Console Redirection Table to enable (i.a.) Microsoft Windows Emergency Management Services (EMS) over the serial port. This patch replaces the Spcr.asl file which described the SPCR table in TDL format with Spcr.aslc which allows more flexibility by way of permitting the use of PCDs. This means the serial port usage can be modified at build. Evan Lloyd (1): Platforms/ARM/Juno: Use PCDs for SPCR info Sami Mujawar (1): Platforms/ARM/Juno: Acpi - update SPCR to aslc. Platforms/ARM/Juno/ArmJuno.dsc | 1 + Platforms/ARM/Juno/AcpiTables/AcpiTables.inf | 12 ++- Platforms/ARM/Juno/AcpiTables/Spcr.asl | 73 --------------- Platforms/ARM/Juno/AcpiTables/Spcr.aslc | 99 ++++++++++++++++++++ 4 files changed, 110 insertions(+), 75 deletions(-) delete mode 100644 Platforms/ARM/Juno/AcpiTables/Spcr.asl create mode 100644 Platforms/ARM/Juno/AcpiTables/Spcr.aslc -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

[PATCH v5 00/22] Marvell Armada7040 SoC support

by Marcin Wojtas

Hello, Here's v5 version of the support. It's rebased on top of newest master branch and comprise fixes from the latest review. Patches are also available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v4 -> v5 * Add ParsePcdLib - Library created in order to parse PCD strings - it makes support for multi-controller easier to implement * I2c - Introduce multi-bus support - Remove comments regarding GUID-slave address dependency - Add FIXME comment about no-restart dual definition * eeprom command - Enable selecting I2C bus - Add FIXME comment about no-restart dual definition * Spi - Fix writing procedure - Rename protocol to MARVELL_SPI_MASTER_PROTOCOL * General - Remove commented-out, unused lines v3 -> v4 * Update license messages - Unify - Add "Based on" statement were needed - Wrap every message at 80 characters - Add Marvell copyrights * Fix namings - All protocol/file names updated as suggested in review * Clean-up - Remove unneded blank lines and spaces - Fix typos * Add "Reviewed by" for currently accepted patches * Add support for new platform - Armada70x0 - Remove support for old platforms Apn806 and Armada7040_rz - Armada70x0 is based on Armada7040_rz with silicone fixes and improvements - No changes on drivers/libraries caused by this change - Update commit logs in whole tree * MppLib - Fix issue with writing to uninitialized memory * I2c and eeprom command - Remove dependency on BdsLibConnectAll call - I2c stack is connected only if eeprom command is executed and only in case it wasn't done before - gBS->ConnectController() used * BdsLib - Remove import of BdsLib - After rebase on top of new edk2, extra BdsLibConnectAll call isn't necessary (actually for now no BdsLibConnectAll is needed at all for our platform support) * sf command - Remove inclusion of relative path - Necessary macro now defined in globally exported file * RamDisk driver - Drop patch with this feature - As long as there is no possibility to format RamDisk with FAT, driver is not useful on Armada70x0 * fupdate command - Fix issue with "bad checksum" v2 -> v3 * Decrease binary size * Fupdate command - Remove regression - replace ShellExecute with RunShellCommand - Improve error paths * Add proper DEBUG library and change error print levels v1 -> v2 * Fix "may be used uninitialized" variables issue, branch compiles both with DEBUG and RELEASE flags * Remove I2C_FLAG_NORESTART dependency - replace it with local definition * Remove Marvell UART Library: - DW8250 IP has programming interface compatible with NS-16550. Since in edk2 there is support for 16550, internal library is unnecessary. - /Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf is used instead * RamDisk driver: - Remove old driver imported from EFI TOOLKIT 2.0 - Replace it with new MdeModulePkg/Universal/Disk/RamDiskDxe from edk2 - Lack of FAT formatting issue emerged * Add explicit dependency on IoLib in Drivers/Spi/SpiDxe.inf * Add poster's "Signed-off-by" registry to every commit message * Move to 05.04.2016 HEAD of edk2/master - Update CpuExceptionHandlerLib within OPP. Bartosz Szczepanek (3): Drivers/I2c: Create MvI2cDxe driver Drivers/I2c: Add MvEeprom driver Aplications/Eeprom: Add 'eeprom' command to shell Jan Dąbroś (17): Platforms/Marvell: Create MppLib Platforms/Marvell: Armada: Enable MppLib on Armada70x0 platform Platforms/Marvell: Create ParsePcdLib Platforms/Marvell: Enable ParsePcdLib for Armada70x0 platform Platforms/Marvell: Enable I2C driver on Armada70x0 platform Plaforms/Marvell: Enable EEPROM driver on Armada70x0 platform Platforms/Marvell: Enable 'eeprom' command on Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_MASTER_PROTOCOL Drivers/Spi: Add Spi master driver Platforms/Marvell: Enable Spi master driver for Armada70x0 platform Platforms/Marvell: Add MARVELL_SPI_FLASH_PROTOCOL Drivers/Spi: Implement Spi flash driver Platforms/Marvell: Enable Spi flash driver for Armada70x0 platform Applications/SpiTool: Add 'sf' command utility Platforms/Marvell: Enable 'sf' command on Armada70x0 platform Applications/FirmwareUpdate: Add 'fupdate' comand to shell Platforms/Marvell: Enable 'fupdate' command on Armada70x0 platform Yehuda Yitschak (2): Platforms/Marvell: Add initial support for Armada70x0 SOC lib Platforms/Marvell: Add support for Armada70x0 platform Applications/EepromCmd/EepromCmd.c | 397 +++++++++++ Applications/EepromCmd/EepromCmd.inf | 71 ++ Applications/EepromCmd/EepromCmd.uni | Bin 0 -> 6816 bytes Applications/FirmwareUpdate/FUpdate.c | 447 +++++++++++++ Applications/FirmwareUpdate/FUpdate.inf | 68 ++ Applications/FirmwareUpdate/FUpdate.uni | Bin 0 -> 5838 bytes Applications/SpiTool/SpiFlashCmd.c | 526 +++++++++++++++ Applications/SpiTool/SpiFlashCmd.inf | 75 +++ Applications/SpiTool/SpiFlashCmd.uni | Bin 0 -> 7216 bytes Documentation/Marvell/Drivers/EepromDriver.txt | 96 +++ Documentation/Marvell/Drivers/I2cDriver.txt | 64 ++ Documentation/Marvell/Drivers/SpiDriver.txt | 116 ++++ Documentation/Marvell/PortingGuide/I2c.txt | 20 + Documentation/Marvell/PortingGuide/Mpp.txt | 48 ++ Documentation/Marvell/PortingGuide/Spi.txt | 15 + Documentation/Marvell/PortingGuide/SpiFlash.txt | 23 + Drivers/I2c/Devices/MvEeprom/MvEeprom.c | 297 ++++++++ Drivers/I2c/Devices/MvEeprom/MvEeprom.h | 97 +++ Drivers/I2c/Devices/MvEeprom/MvEeprom.inf | 70 ++ Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 743 +++++++++++++++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 263 ++++++++ Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 75 +++ Drivers/Spi/Devices/MvSpiFlash.c | 531 +++++++++++++++ Drivers/Spi/Devices/MvSpiFlash.h | 132 ++++ Drivers/Spi/Devices/MvSpiFlash.inf | 67 ++ Drivers/Spi/MvSpiDxe.c | 379 +++++++++++ Drivers/Spi/MvSpiDxe.h | 145 ++++ Drivers/Spi/MvSpiDxe.inf | 66 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 448 +++++++++++++ Platforms/Marvell/Armada/Armada70x0.dsc | 97 +++ Platforms/Marvell/Armada/Armada70x0.fdf | 269 ++++++++ .../Armada70x0Lib/AArch64/ArmPlatformHelper.S | 66 ++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 155 +++++ .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 69 ++ .../Library/Armada70x0Lib/Armada70x0LibMem.c | 93 +++ Platforms/Marvell/Include/Library/MppLib.h | 42 ++ Platforms/Marvell/Include/Library/ParsePcdLib.h | 46 ++ Platforms/Marvell/Include/Protocol/Eeprom.h | 60 ++ Platforms/Marvell/Include/Protocol/Spi.h | 105 +++ Platforms/Marvell/Include/Protocol/SpiFlash.h | 113 ++++ Platforms/Marvell/Library/MppLib/MppLib.c | 163 +++++ Platforms/Marvell/Library/MppLib/MppLib.inf | 107 +++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.c | 228 +++++++ .../Marvell/Library/ParsePcdLib/ParsePcdLib.inf | 50 ++ Platforms/Marvell/Marvell.dec | 136 ++++ 45 files changed, 7078 insertions(+) create mode 100644 Applications/EepromCmd/EepromCmd.c create mode 100644 Applications/EepromCmd/EepromCmd.inf create mode 100644 Applications/EepromCmd/EepromCmd.uni create mode 100644 Applications/FirmwareUpdate/FUpdate.c create mode 100644 Applications/FirmwareUpdate/FUpdate.inf create mode 100644 Applications/FirmwareUpdate/FUpdate.uni create mode 100644 Applications/SpiTool/SpiFlashCmd.c create mode 100644 Applications/SpiTool/SpiFlashCmd.inf create mode 100644 Applications/SpiTool/SpiFlashCmd.uni create mode 100644 Documentation/Marvell/Drivers/EepromDriver.txt create mode 100644 Documentation/Marvell/Drivers/I2cDriver.txt create mode 100644 Documentation/Marvell/Drivers/SpiDriver.txt create mode 100644 Documentation/Marvell/PortingGuide/I2c.txt create mode 100644 Documentation/Marvell/PortingGuide/Mpp.txt create mode 100644 Documentation/Marvell/PortingGuide/Spi.txt create mode 100644 Documentation/Marvell/PortingGuide/SpiFlash.txt create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.c create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.h create mode 100644 Drivers/I2c/Devices/MvEeprom/MvEeprom.inf create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.c create mode 100644 Drivers/I2c/MvI2cDxe/MvI2cDxe.h create mode 100755 Drivers/I2c/MvI2cDxe/MvI2cDxe.inf create mode 100755 Drivers/Spi/Devices/MvSpiFlash.c create mode 100755 Drivers/Spi/Devices/MvSpiFlash.h create mode 100644 Drivers/Spi/Devices/MvSpiFlash.inf create mode 100755 Drivers/Spi/MvSpiDxe.c create mode 100644 Drivers/Spi/MvSpiDxe.h create mode 100644 Drivers/Spi/MvSpiDxe.inf create mode 100644 Platforms/Marvell/Armada/Armada.dsc.inc create mode 100644 Platforms/Marvell/Armada/Armada70x0.dsc create mode 100644 Platforms/Marvell/Armada/Armada70x0.fdf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf create mode 100644 Platforms/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c create mode 100644 Platforms/Marvell/Include/Library/MppLib.h create mode 100644 Platforms/Marvell/Include/Library/ParsePcdLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Eeprom.h create mode 100644 Platforms/Marvell/Include/Protocol/Spi.h create mode 100644 Platforms/Marvell/Include/Protocol/SpiFlash.h create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.c create mode 100644 Platforms/Marvell/Library/MppLib/MppLib.inf create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.c create mode 100644 Platforms/Marvell/Library/ParsePcdLib/ParsePcdLib.inf create mode 100644 Platforms/Marvell/Marvell.dec -- 1.8.3.1

8 years, 5 months

[PATCH] Platforms/ARM: Juno: PL011 PCD changes

by evan.lloyd＠arm.com

From: Sami Mujawar <sami.mujawar(a)arm.com> The generic PL011 driver has been updated to allow for UARTs on a board having different clock sources (as is the case on Juno). See "ArmPlatformPkg: Add support to configure PL011 UART clock" This change modifies the Juno code to use the new driver options. By replacing Pl011UartInteger with Pl011UartClKInHz, the driver can be used with different serial ports. This replaces an erroneous calculated value with a TRM defined clock rate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar(a)arm.com> Signed-off-by: Evan Lloyd <evan.lloyd(a)arm.com> --- Notes: PL011_v2: - Commit message updated to clarify [Ryan Harking] PL011_v3: - No code update, just adding a link for Leif [Leif Lindholm] Code available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/PL011_v3 Platforms/ARM/Juno/ArmJuno.dsc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 3626dfb6e5834f36d136214550ecfde7ed41e4e5..490e08eb9248a4c63ae4580a55037624be435d6c 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -122,8 +122,7 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 - gArmPlatformTokenSpaceGuid.PL011UartInteger|4 - gArmPlatformTokenSpaceGuid.PL011UartFractional|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|7372800 gArmPlatformTokenSpaceGuid.PL011UartInterrupt|115 ## PL031 RealTimeClock -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

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