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811 discussions

[PATCH 0/2] Platforms/ARM/Juno/ACPI: Correct MADT table

by evan.lloyd＠arm.com

From: Evan Lloyd <evan.lloyd(a)arm.com> These minor changes correct naming/version problems in the Juno MADT Acpi table. Thee resultant code is available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/MADT_v1 Alexei (2): Platforms/ARM/Juno/ACPI: Fix name of MADT structure Platforms/ARM/Juno/ACPI: Fix MADT table Platforms/ARM/Juno/AcpiTables/Madt.aslc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

[PATCH 0/2] Updates to Juno DBG2 Acpi table

by evan.lloyd＠arm.com

From: Evan Lloyd <evan.lloyd(a)arm.com> These updates modify the DBG2 table to AslC instead of TDL, and add PCDs to allow build time customisation. Thee resultant code is available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/DBG2_v3 Evan Lloyd (2): Platforms/ARM/Juno: Acpi - update DBG2 to aslc. Platforms/ARM/Juno: Use PCDs for Acpi DBG2 Platforms/ARM/Juno/ArmJuno.dsc | 6 +- Platforms/ARM/Juno/AcpiTables/AcpiTables.inf | 4 +- Platforms/ARM/Juno/AcpiTables/Dbg2.asl | 72 --------------- Platforms/ARM/Juno/AcpiTables/Dbg2.aslc | 92 ++++++++++++++++++++ 4 files changed, 100 insertions(+), 74 deletions(-) delete mode 100644 Platforms/ARM/Juno/AcpiTables/Dbg2.asl create mode 100644 Platforms/ARM/Juno/AcpiTables/Dbg2.aslc -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

[PATCH v5 0/4] arm64, xen: add xen_boot support into grup-mkconfig

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> This patchset add xen_boot support into grup-mkconfig for generating xen boot entrances automatically Also update the docs/grub.texi for new xen_boot commands. This patchset has been tested on Foudation model with a bug fix: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00205.html ChangeLog: v5: Update the introduction of xen_module commands in docs/grub.texi, according to the suggestion from Julien Grall v4: http://lists.gnu.org/archive/html/grub-devel/2016-05/ according to the XSM loading mechanism of Xen(upstreamed), update the introduction of xen_module commands in docs/grub.texi v3: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00314.html reorder the patches update the introduction of xen_module commands in docs/grub.texi v2: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00282.html add "--nounzip" option support in xen_module use "feature_xen_boot" instead of "grub_xen_boot" update the introduction of xen boot commands in docs/grub.texi v1 :first upstream patchset: http://lists.gnu.org/archive/html/grub-devel/2016-02/msg00264.html Fu Wei (4): i386,xen: Add xen_hypervisor and xen_module aliases for i386 arm64: add "--nounzip" option support in xen_module command * util/grub.d/20_linux_xen.in: Add xen_boot command support arm64: update the introduction of xen boot commands in docs/grub.texi docs/grub.texi | 32 +++++++++----------------------- grub-core/loader/arm64/xen_boot.c | 17 +++++++++++++++++ grub-core/loader/i386/xen.c | 7 +++++++ grub-core/normal/main.c | 2 +- util/grub.d/20_linux_xen.in | 13 ++++++++++--- 5 files changed, 44 insertions(+), 27 deletions(-) -- 2.5.5

8 years, 5 months

PCI performance issue

by Shaveta Leekha

Hi, I have been working on PCI controller driver performance (Root Bridge) for my ARMv8 platform. I had integrated my PciHostBridgeDxe code with MdeModulePkg/Bus/Pci/PciBusDxe. Have followed PCI Host bridge resource allocation and Root bridge IO protocol, as used in some other existing PCI root bridge driver. My concern here is that: Tftp using PCI interface is painfully slow. It takes around 10 mins to transfer a 30MB file over PCI NIC card using Tftp Has anyone observed the slowness in network transfer using PCI interface? I couldn't figure out any bottlenecks in PCI root bridge driver( it uses ArmDmaLib for Allocate, Free, Map and UnMap) nor does PCIBUS driver seems to have. Can the slowness be Network stack (like SNP, MNP and other protocols) or E1000 driver code or TFTP command code? Any pointer for the same would be really helpful!! Thanks in advance for your time! Best regards, Shaveta

8 years, 6 months

shortage of ARM maintainers next week

by Leif Lindholm

Hi all, Just thought I should give a heads up that both myself and Ard will be unavailable next week. I will be back on the 25 July, and Ard a week after that. Apologies for any inconvenience. Regards, Leif

8 years, 6 months

[PATCH v2 0/2] Lan9x driver fixes

by Daniil Egranov

The patches are fixing issues with ARP messages and TX recycle buffer overflow. Daniil Egranov (2): OpenPlatformPkg/Lan91xDxe: Fixed ARP broadst message handling OpenPlatformPkg/Lan91xDxe: Fixed TX recycle buffer overflow Drivers/Net/Lan91xDxe/Lan91xDxe.c | 116 +++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 57 deletions(-) -- 2.7.4

8 years, 6 months

[PATCHv4 0/2] ArmJuno: Correct AXI<->PCI translations

by Jeremy Linton

The PCIe PIO translation is incorrect on the Juno, correct that. While we are updating that module correct the comments to more accurately reflect the code and what is actually happening. Jeremy Linton (2): ArmJuno: fix Juno PIO host bridge mapping ArmJuno: Correct AXI->PCIe translation comments .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.4.11

8 years, 6 months

[PATCH] Platforms/Styx: add FvNameGuid to FvMain FV

by Ard Biesheuvel

This adds name GUIDs to the Styx FDFs so that DevicePath references to its contents (i.e., for the UiApp and Shell UEFI applications) are emitted unambiguously rather than as MemoryMapped()/ device path nodes, whose values may change between boots (e.g., if the amount of memory changes, or if the firmware image is updated). Having stable boot entries is preferable, given that the generic BDS code autogenerates entries for the UI app and the shell, but does not clean up the stale outdated ones. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf | 1 + Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf index 148c0a694f16..3b2116756439 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.fdf @@ -70,6 +70,7 @@ FV = STYX_EFI ################################################################################ [FV.FvMain] +FvNameGuid = 72b41709-8499-4841-a383-f432de6fce2a BlockSize = 0x40 NumBlocks = 0 # This FV gets compressed so make it just big enough FvAlignment = 16 # FV alignment and FV attributes setting. diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf index 04894d5aa2fd..02e92434813c 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.fdf @@ -70,6 +70,7 @@ FV = STYX_EFI ################################################################################ [FV.FvMain] +FvNameGuid = 94f067ae-2aa6-4b30-aa07-4e47fe518bb8 BlockSize = 0x40 NumBlocks = 0 # This FV gets compressed so make it just big enough FvAlignment = 16 # FV alignment and FV attributes setting. -- 1.9.1

8 years, 6 months

[PATCH v3] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Further, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 6 months

[PATCH] ArmJuno: fix Juno PIO host bridge mapping

by Jeremy Linton

The Juno PIO mapping is 8M, so it should be using 32-bit PIO address translation. Futher, PIO addresses should start at 0 and be translated to/from the ARM MMIO region. Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- .../ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5..1774e7d 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation"); - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); // Setup the PCI Configuration Registers // Offset 0a: SubClass 04 PCI-PCI Bridge @@ -82,7 +84,7 @@ HWPciRbInit ( PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations + // PCIE Window 0 -> AXI4 Master 0 Address Translations // TranslationTable = VEXPRESS_ATR_PCIE_WIN0; @@ -107,9 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); TranslationTable += PCI_ATR_ENTRY_SIZE; - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + // PCI IO Support, the PIO space is translated from the ARM MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); TranslationTable += PCI_ATR_ENTRY_SIZE; // PCI MEM32 Support -- 2.4.11

8 years, 6 months

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