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[PATCH] [RESEND] Platforms/ARM/Juno: Add support for ACPI 6.0 LPI(Low Power Idle) states

by Sudeep Holla

ACPI 6.0 introduced LPI(Low Power Idle) states that provides an alternate method to describe processor idle states. LPI extensions leverages the processor container device(again introduced in ACPI 6.0) allowing to express which parts of the system are affected by a given LPI state. It defines the local power states for each node in a hierarchical processor topology. The OSPM can use _LPI object to select a local power state for each level of processor hierarchy in the system. This patch adds LPI support on Juno. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Cc: Evan Lloyd <Evan.Lloyd(a)arm.com> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/Dsdt.asl | 232 ++++++++++++++++++++++++++++++--- 1 file changed, 213 insertions(+), 19 deletions(-) Hi Lief, Assuming Evan has lost the patches during his holidays, I am resending it. The support in the kernel is now added(latest mainline as of today) and is enabled in defconfig. It's easy to test, just examine the sysfs entries: /sys/devices/system/cpu/cpu*/cpuidle/state*/desc - Describes the cpuidle state /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time} - Should keep ticking with time signifying that the idle states are entered and exited correctly Regards, Sudeep diff --git a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl index c324ded471f2..07e32bae21f8 100644 --- a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl +++ b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl @@ -19,29 +19,223 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O // // A57x2-A53x4 Processor declaration // - Device(CPU0) { // A53-0: Cluster 1, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 0) + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { + If (!(Arg1 == One)) { + STS0 &= ~0x1F + STS0 |= 0x0A + } Else { + If ((CAP0 & 0x100)) { + CAP0 &= ~0x100 /* No support for OS Initiated LPI */ + STS0 &= ~0x1F + STS0 |= 0x12 + } + } + } Else { + STS0 &= ~0x1F + STS0 |= 0x06 + } + Return (Arg3) } - Device(CPU1) { // A53-1: Cluster 1, Cpu 1 - Name(_HID, "ACPI0007") + Device (CLU0) { // Cluster0 state + Name(_HID, "ACPI0010") Name(_UID, 1) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU0) { // A57-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU1) { // A57-1: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } - Device(CPU2) { // A53-2: Cluster 1, Cpu 2 - Name(_HID, "ACPI0007") + Device (CLU1) { // Cluster1 state + Name(_HID, "ACPI0010") Name(_UID, 2) - } - Device(CPU3) { // A53-3: Cluster 1, Cpu 3 - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { // A57-0: Cluster 0, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { // A57-1: Cluster 0, Cpu 1 - Name(_HID, "ACPI0007") - Name(_UID, 5) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU2) { // A53-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU3) { // A53-1: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU4) { // A53-2: Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU5) { // A53-3: Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } // -- 2.7.4

9 years

[PATCH] Platforms/ARM: fix gtdt.asl for VExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc | 128 ++++++++++++++++++++++------ 1 file changed, 101 insertions(+), 27 deletions(-) diff --git a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc index 142249f..8ed9a31 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Gtdt.aslc @@ -19,21 +19,70 @@ #include <Library/PcdLib.h> #include <IndustryStandard/Acpi61.h> -#define SECURE_TIMER_EL1_GSIV 0x1D -#define NON_SECURE_TIMER_EL1_GSIV 0x1E -#define VIRTUAL_TIMER_GSIV 0x1B -#define NON_SECURE_EL2_GSIV 0x1A +#define FVP_SYSTEM_TIMER_BASE_ADDRESS 0x000000002a430000 +#define FVP_CNT_READ_BASE_ADDRESS 0x000000002a800000 -#define GT_BLOCK_CTL_BASE 0x000000002A810000 -#define GT_BLOCK_FRAME1_CTL_BASE 0x000000002A820000 -#define GT_BLOCK_FRAME1_GSIV 0x29 +#define FVP_SECURE_TIMER_EL1_GSIV 0x1D +#define FVP_NON_SECURE_TIMER_EL1_GSIV 0x1E +#define FVP_VIRTUAL_TIMER_GSIV 0x1B +#define FVP_NON_SECURE_EL2_GSIV 0x1A + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_SECURE EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY +#define GTDT_TIMER_NON_SECURE 0 + +#define FVP_GTDT_GTIMER_FLAGS (GTDT_TIMER_NON_SECURE | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED) + +#define FVP_PLATFORM_TIMER_COUNT 2 +#define FVP_TIMER_FRAMES_COUNT 2 +#define FVP_WATCHDOG_COUNT 1 + +#define FVP_GT_BLOCK_CTL_BASE 0x000000002A810000 +#define FVP_GT_BLOCK_FRAME0_CTL_BASE 0x000000002A820000 +#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME0_GSIV 0x39 + +#define FVP_GT_BLOCK_FRAME1_CTL_BASE 0x000000002A830000 +#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define FVP_GT_BLOCK_FRAME1_GSIV 0x3A + +#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTX_TIMER_LEVEL_TRIGGERED 0 +#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTX_TIMER_ACTIVE_HIGH 0 + +#define FVP_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED) + +#define GTX_TIMER_SECURE EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_LOSE_CONTEXT 0 + +#define FVP_GTX_COMMON_FLAGS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE) + +#define FVP_SBSA_WATCHDOG_REFRESH_BASE 0x000000002a450000 +#define FVP_SBSA_WATCHDOG_CONTROL_BASE 0x000000002a440000 +#define FVP_SBSA_WATCHDOG_GSIV 0x3B + +#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE +#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0 +#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY +#define SBSA_WATCHDOG_ACTIVE_HIGH 0 +#define SBSA_WATCHDOG_SECURE EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER +#define SBSA_WATCHDOG_NON_SECURE 0 + +#define FVP_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED) #pragma pack (1) typedef struct { EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock; - EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[1]; + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[FVP_TIMER_FRAMES_COUNT]; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[FVP_WATCHDOG_COUNT]; } FVP_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () @@ -45,27 +94,28 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { FVP_GENERIC_TIMER_DESCRIPTION_TABLES, EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress + FVP_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved - SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 SecurePL1TimerFlags - NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL1TimerFlags - VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 VirtualTimerFlags - NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV - EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE, // UINT32 NonSecurePL2TimerFlags - 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress - 1, // UINT32 PlatformTimerCount + FVP_SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FVP_NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FVP_VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FVP_NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV + FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + FVP_CNT_READ_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress + FVP_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { EFI_ACPI_6_1_GTDT_GT_BLOCK, // UINT8 Type sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT16 Length - + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE), + + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + FVP_TIMER_FRAMES_COUNT, EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved - GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase - 1, // UINT32 GTBlockTimerCount + FVP_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase + FVP_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset }, { @@ -74,13 +124,37 @@ FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] - GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX - 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX - GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV - 0, // UINT32 GTxPhysicalTimerFlags + FVP_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags 0, // UINT32 GTxVirtualTimerGSIV 0, // UINT32 GTxVirtualTimerFlags - 0 // UINT32 GTxCommonFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + }, + { + 1, // UINT8 GTFrameNumber + {EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3] + FVP_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX + FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX + FVP_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV + FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + FVP_GTX_COMMON_FLAGS // UINT32 GTxCommonFlags + } + }, + { + { + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + FVP_SBSA_WATCHDOG_REFRESH_BASE, // UINT64 RefreshFramePhysicalAddress + FVP_SBSA_WATCHDOG_CONTROL_BASE, // UINT64 WatchdogControlFramePhysicalAddress + FVP_SBSA_WATCHDOG_GSIV, // UINT32 WatchdogTimerGSIV + FVP_SBSA_WATCHDOG_FLAGS // UINT32 WatchdogTimerFlags } } }; -- 2.5.5

9 years

[PATCH 0/3] Armada 7040 network support

by Marcin Wojtas

Hi, Since serdes, mdio and phy support of Armada 7040 has been integrated to the tree, here is another part of the platform. This short patchset comprise only adding and enabling driver for a single network controller with multi-port. It consumes Simple Network Protocol and registers as many of its instances as defined in PCD's. Please refer to porting guide and the commit logs for more details. The driver itself is not huge and it makes use of the OS-independent library obtained from Marvell, comprising pure HW configuration. Drivers/Net/Pp2Dxe/Pp2Dxe.h is therefore a glue between the library and UEFI environment. The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Bartosz Szczepanek (3): Drivers/Net: Import mvpp2_lib Drivers/Net: Create Pp2Dxe driver Platforms/Marvell: Enable Pp2Dxe driver on Armada70x0 platform Documentation/Marvell/PortingGuide/Pp2.txt | 59 + Drivers/Net/Pp2Dxe/Pp2Dxe.c | 1190 ++++++++ Drivers/Net/Pp2Dxe/Pp2Dxe.h | 530 ++++ Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 91 + Drivers/Net/Pp2Dxe/mvpp2_lib.c | 4299 ++++++++++++++++++++++++++++ Drivers/Net/Pp2Dxe/mvpp2_lib.h | 2362 +++++++++++++++ Platforms/Marvell/Armada/Armada.dsc.inc | 1 + Platforms/Marvell/Armada/Armada70x0.dsc | 18 +- Platforms/Marvell/Armada/Armada70x0.fdf | 1 + Platforms/Marvell/Marvell.dec | 16 + 10 files changed, 8566 insertions(+), 1 deletion(-) create mode 100644 Documentation/Marvell/PortingGuide/Pp2.txt create mode 100644 Drivers/Net/Pp2Dxe/Pp2Dxe.c create mode 100644 Drivers/Net/Pp2Dxe/Pp2Dxe.h create mode 100644 Drivers/Net/Pp2Dxe/Pp2Dxe.inf create mode 100644 Drivers/Net/Pp2Dxe/mvpp2_lib.c create mode 100644 Drivers/Net/Pp2Dxe/mvpp2_lib.h -- 1.8.3.1

9 years

[PATCH v2] OpenPlatformPkg/MarvellYukonDxe: Add EBC build support

by Daniil Egranov

Changelog: v1->v2: Removing platform dependencies and improving EBC code performance by replacing the following functions with their Boot Service versions: CopyMem() -> gBS->CopyMem() AllocateZeroPool() -> gBS->AllocatePool() + gBS->SetMem() ZeroMem() -> gBS->SetMem() FreePool() -> gBS->FreePool() v1: The patch removes dependencies on platform specific libraries and direct calls to functions with a platform specific implementation. Added MarvelYukonDxe.dsc for platform independent builds including EBC: build -a <target_architecture> \ -p OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc \ -m OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf \ -b DEBUG -t <toolchain> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov(a)arm.com> --- NOTE: This patch is based on "OpenPlatformPkg/MarvellYukonDxe: Marvell Yukon NIC driver" v4 patch. This patch includes same fix as Alan Ott's "[PATCH 1/7] Drivers/Net/MarvellYukon: Remove ARM-specific include" patch. Depending on the apply order, the patch for DeviceConfig.c should be ignored in one of the cases. Drivers/Net/MarvellYukonDxe/DeviceConfig.c | 38 ++++---- Drivers/Net/MarvellYukonDxe/DriverBinding.c | 27 +++--- Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc | 88 ++++++++++++++++++ Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf | 1 - Drivers/Net/MarvellYukonDxe/Snp.c | 30 +++--- Drivers/Net/MarvellYukonDxe/e1000phy.c | 14 ++- Drivers/Net/MarvellYukonDxe/if_msk.c | 116 ++++++++++++++---------- 7 files changed, 217 insertions(+), 97 deletions(-) create mode 100644 Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc diff --git a/Drivers/Net/MarvellYukonDxe/DeviceConfig.c b/Drivers/Net/MarvellYukonDxe/DeviceConfig.c index c64f82a..0aec7be 100644 --- a/Drivers/Net/MarvellYukonDxe/DeviceConfig.c +++ b/Drivers/Net/MarvellYukonDxe/DeviceConfig.c @@ -12,7 +12,6 @@ * **/ -#include <ArmPlatform.h> #include <Protocol/PciIo.h> #include <IndustryStandard/Pci.h> #include <Library/IoLib.h> @@ -198,12 +197,16 @@ DeviceConfigSupported ( return EFI_UNSUPPORTED; } - ConfigHandles = AllocateZeroPool (sizeof (EFI_HANDLE) * HandleCount); - if (ConfigHandles == NULL) { - FreePool(HandleBuffer); - return EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (EFI_HANDLE) * HandleCount, + (VOID**) &ConfigHandles); + if (EFI_ERROR (Status)) { + gBS->FreePool(HandleBuffer); + return Status; } + gBS->SetMem (ConfigHandles, sizeof (EFI_HANDLE) * HandleCount, 0); + // Loop through all device handles and probe for the Marvel Yukon for (HIndex = 0; HIndex < HandleCount; ++HIndex) { @@ -228,11 +231,13 @@ DeviceConfigSupported ( Status = EFI_SUCCESS; if (*RecordCount != 0) { - *Buffer = - AllocateZeroPool (sizeof (EFI_DEVICE_CONFIGURATION_RECORD) * (*RecordCount)); - if (*Buffer == NULL) { - Status = EFI_OUT_OF_RESOURCES; - } else { + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (EFI_DEVICE_CONFIGURATION_RECORD) * (*RecordCount), + (VOID**) &(*Buffer)); + if (!EFI_ERROR (Status)) { + gBS->SetMem (Buffer, + sizeof (EFI_DEVICE_CONFIGURATION_RECORD) * (*RecordCount), + 0); for (RIndex = 0; RIndex < *RecordCount; ++RIndex) { (*Buffer)[RIndex].Controller = ConfigHandles[RIndex]; (*Buffer)[RIndex].SupportedConfigs = 0; @@ -247,8 +252,8 @@ DeviceConfigSupported ( Status = EFI_UNSUPPORTED; } - FreePool(HandleBuffer); - FreePool(ConfigHandles); + gBS->FreePool(HandleBuffer); + gBS->FreePool(ConfigHandles); return Status; } @@ -281,10 +286,11 @@ DeviceConfigGet ( Status = EFI_UNSUPPORTED; if (ConfigType == EfiConfigMacAddress) { - MacAddress = AllocateZeroPool (sizeof (EFI_MAC_ADDRESS)); - if (MacAddress == NULL) { - Status = EFI_OUT_OF_RESOURCES; - } else { + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (EFI_MAC_ADDRESS), + (VOID**) &MacAddress); + if (!EFI_ERROR (Status)) { + gBS->SetMem (MacAddress, sizeof (EFI_MAC_ADDRESS), 0); Status = ConfigMACAddress (Controller, TRUE, MacAddress); if (!EFI_ERROR (Status)) { *Buffer = MacAddress; diff --git a/Drivers/Net/MarvellYukonDxe/DriverBinding.c b/Drivers/Net/MarvellYukonDxe/DriverBinding.c index 98dd991..428ffee 100644 --- a/Drivers/Net/MarvellYukonDxe/DriverBinding.c +++ b/Drivers/Net/MarvellYukonDxe/DriverBinding.c @@ -107,25 +107,25 @@ MarvellYukonDriverStart ( { EFI_STATUS Status; - UINTN LengthInBytes; EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; MAC_ADDR_DEVICE_PATH MacDeviceNode; VOID *ChildPciIo; YUKON_DRIVER *YukonDriver; - LengthInBytes = sizeof (*YukonDriver); - YukonDriver = (YUKON_DRIVER *)AllocateZeroPool (sizeof (YUKON_DRIVER)); - if (YukonDriver == NULL) { - DEBUG ((EFI_D_ERROR, "Marvell Yukon: AllocateZeroPool() failed with Status = %r\n", EFI_OUT_OF_RESOURCES)); - return EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (YUKON_DRIVER), + (VOID**) &YukonDriver); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Marvell Yukon: AllocatePool() failed with Status = %r\n", EFI_OUT_OF_RESOURCES)); + return Status; } + gBS->SetMem (YukonDriver, sizeof (YUKON_DRIVER), 0); EfiInitializeLock (&YukonDriver->Lock, TPL_NOTIFY); // // Set the structure signature // - ZeroMem (YukonDriver, LengthInBytes); YukonDriver->Signature = YUKON_DRIVER_SIGNATURE; Status = gBS->OpenProtocol ( @@ -184,7 +184,7 @@ MarvellYukonDriverStart ( return Status; } - ZeroMem (&MacDeviceNode, sizeof (MAC_ADDR_DEVICE_PATH)); + gBS->SetMem (&MacDeviceNode, sizeof (MAC_ADDR_DEVICE_PATH), 0); MacDeviceNode.Header.Type = MESSAGING_DEVICE_PATH; MacDeviceNode.Header.SubType = MSG_MAC_ADDR_DP; @@ -205,8 +205,8 @@ MarvellYukonDriverStart ( // // Assign fields for device path // - CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); - CopyMem (&MacDeviceNode.MacAddress, &YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->CopyMem (&MacDeviceNode.MacAddress, &YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS)); MacDeviceNode.IfType = YukonDriver->SnpMode.IfType; YukonDriver->DevicePath = AppendDevicePathNode (ParentDevicePath, &MacDeviceNode.Header); @@ -490,8 +490,11 @@ InitializeMarvellYukonDriver ( if (!EFI_ERROR (Status)) { ControllerHandle = NULL; - if((CfgProtocol = AllocateZeroPool (sizeof (EFI_EMBEDDED_DEVICE_CONFIG_PROTOCOL))) != NULL) { - + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (EFI_EMBEDDED_DEVICE_CONFIG_PROTOCOL), + (VOID**) &CfgProtocol); + if(!EFI_ERROR (Status)) { + gBS->SetMem (CfgProtocol, sizeof (EFI_EMBEDDED_DEVICE_CONFIG_PROTOCOL), 0); InitializeDeviceConfigProtocol(CfgProtocol); Status = gBS->InstallProtocolInterface ( &ControllerHandle, diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc new file mode 100644 index 0000000..718d48c --- /dev/null +++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc @@ -0,0 +1,88 @@ +# +# Copyright (c) 2013-2016, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = MarvellYukonDxe + PLATFORM_GUID = 8391d2d4-63fc-11e6-82d5-7b6c1a2ff410 + PLATFORM_VERSION = 0.96 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/OpenPlatformPkg + SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM|AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + +[LibraryClasses] + # + # Entry point + # + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + # + # UEFI & PI + # + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + # + # Generic Modules + # + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + # + # Misc + # + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + +[LibraryClasses.common.UEFI_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent ARM compiler calls to generic intrinsic functions. + # This library provides the instrinsic functions generated by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + +[LibraryClasses.EBC] + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + +[PcdsFeatureFlag] + +[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.IPF] + +################################################################################################### +# +# Components Section - list of all EDK II Modules included in the build +# +################################################################################################### + +[Components] + OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf index de1059d..cf3e870 100644 --- a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf +++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf @@ -56,7 +56,6 @@ DebugLib TimerLib NetLib - ArmLib DevicePathLib [Pcd] diff --git a/Drivers/Net/MarvellYukonDxe/Snp.c b/Drivers/Net/MarvellYukonDxe/Snp.c index fcc4e31..8166528 100644 --- a/Drivers/Net/MarvellYukonDxe/Snp.c +++ b/Drivers/Net/MarvellYukonDxe/Snp.c @@ -56,12 +56,12 @@ InitializeSNPProtocol ( YukonDriver->SnpMode.IfType = NET_IFTYPE_ETHERNET; YukonDriver->SnpMode.MaxMCastFilterCount = MAX_MCAST_FILTER_CNT; YukonDriver->SnpMode.MCastFilterCount = 0; - ZeroMem (&YukonDriver->SnpMode.MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS)); + gBS->SetMem (&YukonDriver->SnpMode.MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS), 0); // // Set broadcast address // - SetMem (&YukonDriver->SnpMode.BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF); + gBS->SetMem (&YukonDriver->SnpMode.BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF); YukonDriver->SnpMode.MediaPresentSupported = FALSE; YukonDriver->SnpMode.MacAddressChangeable = FALSE; @@ -227,8 +227,8 @@ SnpInitialize ( YukonDriver->SnpMode.MCastFilterCount = 0; YukonDriver->SnpMode.ReceiveFilterSetting = 0; - ZeroMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter); - CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->SetMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter, 0); + gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); Status = mskc_init (); @@ -550,13 +550,13 @@ SnpReceive ( } if (SrcAddr != NULL) { - ZeroMem (SrcAddr, NET_ETHER_ADDR_LEN); - CopyMem (SrcAddr, ((UINT8 *) Buffer) + NET_ETHER_ADDR_LEN, NET_ETHER_ADDR_LEN); + gBS->SetMem (SrcAddr, NET_ETHER_ADDR_LEN, 0); + gBS->CopyMem (SrcAddr, ((UINT8 *) Buffer) + NET_ETHER_ADDR_LEN, NET_ETHER_ADDR_LEN); } if (DestAddr != NULL) { - ZeroMem (DestAddr, NET_ETHER_ADDR_LEN); - CopyMem (DestAddr, ((UINT8 *) Buffer), NET_ETHER_ADDR_LEN); + gBS->SetMem (DestAddr, NET_ETHER_ADDR_LEN, 0); + gBS->CopyMem (DestAddr, ((UINT8 *) Buffer), NET_ETHER_ADDR_LEN); } if (Protocol != NULL) { @@ -899,8 +899,8 @@ SnpShutdown ( YukonDriver->SnpMode.MCastFilterCount = 0; YukonDriver->SnpMode.ReceiveFilterSetting = 0; - ZeroMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter); - CopyMem ( + gBS->SetMem (YukonDriver->SnpMode.MCastFilter, sizeof YukonDriver->SnpMode.MCastFilter, 0); + gBS->CopyMem ( &YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS) @@ -973,7 +973,7 @@ SnpStart ( } YukonDriver->SnpMode.State = EfiSimpleNetworkStarted; - CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->CopyMem (&YukonDriver->SnpMode.CurrentAddress, &YukonDriver->SnpMode.PermanentAddress, sizeof (EFI_MAC_ADDRESS)); YukonDriver->SnpMode.MCastFilterCount = 0; goto ON_EXIT; @@ -1271,7 +1271,7 @@ SnpStop ( mskc_detach (); YukonDriver->SnpMode.State = EfiSimpleNetworkStopped; - ZeroMem (&YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->SetMem (&YukonDriver->SnpMode.CurrentAddress, sizeof (EFI_MAC_ADDRESS), 0); Status = EFI_SUCCESS; goto ON_EXIT; @@ -1402,9 +1402,9 @@ SnpTransmit ( Frame = (ETHER_HEAD*)Buffer; ProtocolNet = NTOHS (*Protocol); - CopyMem (Frame->SrcMac, SrcAddr, NET_ETHER_ADDR_LEN); - CopyMem (Frame->DstMac, DestAddr, NET_ETHER_ADDR_LEN); - CopyMem (&Frame->EtherType, &ProtocolNet, sizeof (UINT16)); + gBS->CopyMem (Frame->SrcMac, SrcAddr, NET_ETHER_ADDR_LEN); + gBS->CopyMem (Frame->DstMac, DestAddr, NET_ETHER_ADDR_LEN); + gBS->CopyMem (&Frame->EtherType, &ProtocolNet, sizeof (UINT16)); } Status = mskc_transmit (BufferSize, Buffer); diff --git a/Drivers/Net/MarvellYukonDxe/e1000phy.c b/Drivers/Net/MarvellYukonDxe/e1000phy.c index d544e88..417aea0 100644 --- a/Drivers/Net/MarvellYukonDxe/e1000phy.c +++ b/Drivers/Net/MarvellYukonDxe/e1000phy.c @@ -56,6 +56,7 @@ #include <Library/MemoryAllocationLib.h> #include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> #include "if_media.h" @@ -119,10 +120,13 @@ e1000_probe_and_attach ( INTN bmsr; EFI_STATUS Status; - mPhySoftc = AllocateZeroPool (sizeof (struct e1000phy_softc)); - if (mPhySoftc == NULL) { - return EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (struct e1000phy_softc), + (VOID**) &mPhySoftc); + if (EFI_ERROR (Status)) { + return Status; } + gBS->SetMem (mPhySoftc, sizeof (struct e1000phy_softc), 0); mPhySoftc->mmd = mmd; @@ -134,7 +138,7 @@ e1000_probe_and_attach ( bmsr = PHY_READ (mPhySoftc, E1000_SR); if (bmsr == 0 || bmsr == 0xffff || (bmsr & (E1000_SR_EXTENDED_STATUS|E1000_SR_MEDIAMASK)) == 0) { /* Assume no PHY at this address. */ - FreePool (mPhySoftc); + gBS->FreePool (mPhySoftc); return EFI_DEVICE_ERROR; } @@ -148,7 +152,7 @@ e1000_probe_and_attach ( Status = e1000phy_probe (&ma); if (EFI_ERROR (Status)) { - FreePool (mPhySoftc); + gBS->FreePool (mPhySoftc); return Status; } diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c index 5e7da93..3dc16b3 100644 --- a/Drivers/Net/MarvellYukonDxe/if_msk.c +++ b/Drivers/Net/MarvellYukonDxe/if_msk.c @@ -247,7 +247,7 @@ msk_phy_readreg ( GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); for (i = 0; i < MSK_TIMEOUT; i++) { - MicroSecondDelay (1); + gBS->Stall (1); val = GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL); if ((val & GM_SMI_CT_RD_VAL) != 0) { val = GMAC_READ_2 (mSoftc, port, GM_SMI_DATA); @@ -275,7 +275,7 @@ msk_phy_writereg ( GMAC_WRITE_2 (mSoftc, port, GM_SMI_DATA, val); GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); for (i = 0; i < MSK_TIMEOUT; i++) { - MicroSecondDelay (1); + gBS->Stall (1); if ((GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) { break; } @@ -437,7 +437,7 @@ msk_rxfilter ( UINT16 mode; INTN port = sc_if->msk_md.port; - ZeroMem (mchash, sizeof (mchash)); + gBS->SetMem (mchash, sizeof (mchash), 0); mode = GMAC_READ_2 (mSoftc, port, GM_RX_CTRL); // if ((ifp->if_flags & IFF_PROMISC) != 0) if ((FilterFlags & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) { @@ -503,11 +503,11 @@ msk_init_rx_ring ( sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; rd = &sc_if->msk_rdata; - ZeroMem (rd->msk_rx_ring, MSK_RX_RING_SZ); + gBS->SetMem (rd->msk_rx_ring, MSK_RX_RING_SZ, 0); prod = sc_if->msk_cdata.msk_rx_prod; for (i = 0; i < MSK_RX_RING_CNT; i++) { rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; - ZeroMem (&rxd->rx_m, sizeof (MSK_DMA_BUF)); + gBS->SetMem (&rxd->rx_m, sizeof (MSK_DMA_BUF), 0); rxd->rx_le = &rd->msk_rx_ring[prod]; Status = msk_newbuf (sc_if, prod); if (EFI_ERROR (Status)) { @@ -538,10 +538,10 @@ msk_init_tx_ring ( sc_if->msk_cdata.msk_tx_cnt = 0; rd = &sc_if->msk_rdata; - ZeroMem (rd->msk_tx_ring, sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT); + gBS->SetMem (rd->msk_tx_ring, sizeof (struct msk_tx_desc) * MSK_TX_RING_CNT, 0); for (i = 0; i < MSK_TX_RING_CNT; i++) { txd = &sc_if->msk_cdata.msk_txdesc[i]; - ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0); txd->tx_le = &rd->msk_tx_ring[i]; } } @@ -604,7 +604,7 @@ msk_newbuf ( return Status; } - ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0); rxd->rx_m.DmaMapping = Mapping; rxd->rx_m.Buf = Buffer; rxd->rx_m.Length = Length; @@ -1024,7 +1024,7 @@ mskc_reset ( } */ // Clear status list - ZeroMem (mSoftc->msk_stat_ring, sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT); + gBS->SetMem (mSoftc->msk_stat_ring, sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT, 0); mSoftc->msk_stat_cons = 0; CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_RST_SET); CSR_WRITE_4 (mSoftc, STAT_CTRL, SC_STAT_RST_CLR); @@ -1140,14 +1140,17 @@ mskc_attach ( struct msk_if_softc *ScIf; mPciIo = PciIo; - mSoftc = AllocateZeroPool (sizeof (struct msk_softc)); - if (mSoftc == NULL) { - return EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (struct msk_softc), + (VOID**) &mSoftc); + if (EFI_ERROR (Status)) { + return Status; } // // Save original PCI attributes // + gBS->SetMem (mSoftc, sizeof (struct msk_softc), 0); Status = mPciIo->Attributes ( mPciIo, EfiPciIoAttributeOperationGet, @@ -1155,7 +1158,7 @@ mskc_attach ( &mSoftc->OriginalPciAttributes ); if (EFI_ERROR (Status)) { - FreePool (mSoftc); + gBS->FreePool (mSoftc); return Status; } @@ -1341,11 +1344,13 @@ mskc_attach ( mskc_setup_rambuffer (); - ScIf = AllocateZeroPool (sizeof (struct msk_if_softc)); - if (ScIf == NULL) { - Status = EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (struct msk_if_softc), + (VOID**) &ScIf); + if (EFI_ERROR (Status)) { goto fail; } + gBS->SetMem (ScIf, sizeof (struct msk_if_softc), 0); mSoftc->msk_if[MSK_PORT_A] = ScIf; Status = msk_attach (MSK_PORT_A); if (EFI_ERROR (Status)) { @@ -1353,7 +1358,7 @@ mskc_attach ( } if (Mac != NULL) { - CopyMem (Mac, &ScIf->MacAddress, sizeof (EFI_MAC_ADDRESS)); + gBS->CopyMem (Mac, &ScIf->MacAddress, sizeof (EFI_MAC_ADDRESS)); } mmd = &ScIf->msk_md; @@ -1364,11 +1369,13 @@ mskc_attach ( } if (mSoftc->msk_num_port > 1) { - ScIf = AllocateZeroPool (sizeof (struct msk_if_softc)); - if (ScIf == NULL) { - Status = EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (struct msk_if_softc), + (VOID**) &ScIf); + if (EFI_ERROR (Status)) { goto fail; } + gBS->SetMem (ScIf, sizeof (struct msk_if_softc), 0); mSoftc->msk_if[MSK_PORT_B] = ScIf; Status = msk_attach (MSK_PORT_B); if (EFI_ERROR (Status)) { @@ -1416,7 +1423,7 @@ RESTORE_PCI_ATTRIBS: mSoftc->OriginalPciAttributes, NULL ); - FreePool (mSoftc); + gBS->FreePool (mSoftc); return Status; } @@ -1453,12 +1460,12 @@ mskc_detach ( if (mSoftc->msk_if[MSK_PORT_A] != NULL) { msk_detach (MSK_PORT_A); - FreePool (mSoftc->msk_if[MSK_PORT_A]); + gBS->FreePool (mSoftc->msk_if[MSK_PORT_A]); mSoftc->msk_if[MSK_PORT_A] = NULL; } if (mSoftc->msk_if[MSK_PORT_B] != NULL) { msk_detach (MSK_PORT_B); - FreePool (mSoftc->msk_if[MSK_PORT_B]); + gBS->FreePool (mSoftc->msk_if[MSK_PORT_B]); mSoftc->msk_if[MSK_PORT_B] = NULL; } @@ -1491,7 +1498,7 @@ mskc_detach ( mSoftc->OriginalPciAttributes, NULL ); - FreePool (mSoftc); + gBS->FreePool (mSoftc); mSoftc = NULL; mPciIo = NULL; @@ -1598,12 +1605,12 @@ msk_txrx_dma_alloc ( // Create DMA maps for Tx buffers. for (i = 0; i < MSK_TX_RING_CNT; i++) { txd = &sc_if->msk_cdata.msk_txdesc[i]; - ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0); } // Create DMA maps for Rx buffers. for (i = 0; i < MSK_RX_RING_CNT; i++) { rxd = &sc_if->msk_cdata.msk_rxdesc[i]; - ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0); } fail: @@ -1645,7 +1652,7 @@ msk_txrx_dma_free ( txd = &sc_if->msk_cdata.msk_txdesc[i]; if (txd->tx_m.DmaMapping) { mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping); - ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0); // We don't own the transmit buffers so don't free them } } @@ -1659,7 +1666,7 @@ msk_txrx_dma_free ( mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf); rxd->rx_m.Buf = NULL; } - ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0); } } } @@ -1733,11 +1740,15 @@ mskc_transmit ( ) { MSK_LINKED_SYSTEM_BUF *LinkedSystemBuf; + EFI_STATUS Status; - LinkedSystemBuf = AllocateZeroPool (sizeof (MSK_LINKED_SYSTEM_BUF)); - if (LinkedSystemBuf == NULL) { - return EFI_OUT_OF_RESOURCES; + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (MSK_LINKED_SYSTEM_BUF), + (VOID**) &LinkedSystemBuf); + if (EFI_ERROR (Status)) { + return Status; } + gBS->SetMem (LinkedSystemBuf, sizeof (MSK_LINKED_SYSTEM_BUF), 0); LinkedSystemBuf->Signature = TX_MBUF_SIGNATURE; // // Add the passed Buffer to the transmit queue. Don't copy. @@ -1773,7 +1784,7 @@ mskc_getstatus ( if(m_head != NULL) { *TxBuf = m_head->SystemBuf.Buf; RemoveEntryList (&m_head->Link); - FreePool (m_head); + gBS->FreePool (m_head); } } } @@ -1959,9 +1970,9 @@ mskc_receive ( } *BufferSize = mBuf->DmaBuf.Length; RemoveEntryList (&mBuf->Link); - CopyMem (Buffer, mBuf->DmaBuf.Buf, *BufferSize); - FreePool(mBuf->DmaBuf.Buf); - FreePool (mBuf); + gBS->CopyMem (Buffer, mBuf->DmaBuf.Buf, *BufferSize); + gBS->FreePool(mBuf->DmaBuf.Buf); + gBS->FreePool (mBuf); return EFI_SUCCESS; } @@ -2006,17 +2017,26 @@ msk_rxeof ( // Reuse old buffer msk_discard_rxbuf (sc_if, cons); } - m_link = AllocateZeroPool (sizeof (MSK_LINKED_DMA_BUF)); - if (m_link != NULL) { + Status = gBS->AllocatePool (EfiBootServicesData, + sizeof (MSK_LINKED_DMA_BUF), + (VOID**) &m_link); + if (!EFI_ERROR (Status)) { + gBS->SetMem (m_link, sizeof (MSK_LINKED_DMA_BUF), 0); rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; m_link->Signature = RX_MBUF_SIGNATURE; - m_link->DmaBuf.Buf = AllocateZeroPool (len); - CopyMem (m_link->DmaBuf.Buf, rxd->rx_m.Buf, len); - m_link->DmaBuf.Length = len; - m_link->DmaBuf.DmaMapping = rxd->rx_m.DmaMapping; - - InsertTailList (&mSoftc->ReceiveQueueHead, &m_link->Link); + Status = gBS->AllocatePool (EfiBootServicesData, + len, + (VOID**) &m_link->DmaBuf.Buf); + if(!EFI_ERROR (Status)) { + gBS->CopyMem (m_link->DmaBuf.Buf, rxd->rx_m.Buf, len); + m_link->DmaBuf.Length = len; + m_link->DmaBuf.DmaMapping = rxd->rx_m.DmaMapping; + + InsertTailList (&mSoftc->ReceiveQueueHead, &m_link->Link); + } else { + DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate DMA buffer. Dropping Frame\n")); + } } else { DEBUG ((EFI_D_NET, "Marvell Yukon: failed to allocate receive buffer link. Dropping Frame\n")); } @@ -2059,7 +2079,7 @@ msk_txeof ( } txd = &sc_if->msk_cdata.msk_txdesc[cons]; mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping); - ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0); // We don't own the transmit buffers so don't free them } @@ -2810,7 +2830,7 @@ msk_stop ( } else { break; } - MicroSecondDelay (1); + gBS->Stall (1); } if (i == MSK_TIMEOUT) { DEBUG ((EFI_D_NET, "Marvell Yukon: Tx BMU stop failed\n")); @@ -2856,7 +2876,7 @@ msk_stop ( if (CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RSL)) == CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RL))) { break; } - MicroSecondDelay (1); + gBS->Stall (1); } if (i == MSK_TIMEOUT) { DEBUG ((EFI_D_NET, "Marvell Yukon: Rx BMU stop failed\n")); @@ -2878,7 +2898,7 @@ msk_stop ( mPciIo->FreeBuffer (mPciIo, EFI_SIZE_TO_PAGES (rxd->rx_m.Length), rxd->rx_m.Buf); rxd->rx_m.Buf = NULL; } - ZeroMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(rxd->rx_m), sizeof (MSK_DMA_BUF), 0); } } @@ -2886,7 +2906,7 @@ msk_stop ( txd = &sc_if->msk_cdata.msk_txdesc[i]; if (txd->tx_m.Buf != NULL) { mPciIo->Unmap (mPciIo, txd->tx_m.DmaMapping); - ZeroMem (&(txd->tx_m), sizeof (MSK_DMA_BUF)); + gBS->SetMem (&(txd->tx_m), sizeof (MSK_DMA_BUF), 0); // We don't own the transmit buffers so don't free them } } -- 2.7.4

9 years

[PATCH] OpenPlatformPkg/MarvellYukonDxe: Add EBC build support

by Daniil Egranov

The patch removes dependencies on platform specific libraries and direct calls to functions with a platform specific implementation. Added MarvelYukonDxe.dsc for platform independent builds including EBC: build -a <target_architecture> \ -p OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc \ -m OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf \ -b DEBUG -t <toolchain> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov(a)arm.com> --- NOTE: This patch is based on "OpenPlatformPkg/MarvellYukonDxe: Marvell Yukon NIC driver" v4 patch. This patch includes same fix as Alan Ott's "[PATCH 1/7] Drivers/Net/MarvellYukon: Remove ARM-specific include" patch. Depending on the apply order, the patch for DeviceConfig.c should be ignored in one of the cases. Drivers/Net/MarvellYukonDxe/DeviceConfig.c | 1 - Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc | 90 +++++++++++++++++++++++++ Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf | 1 - Drivers/Net/MarvellYukonDxe/if_msk.c | 8 +-- 4 files changed, 94 insertions(+), 6 deletions(-) create mode 100644 Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc diff --git a/Drivers/Net/MarvellYukonDxe/DeviceConfig.c b/Drivers/Net/MarvellYukonDxe/DeviceConfig.c index c64f82a..c64c064 100644 --- a/Drivers/Net/MarvellYukonDxe/DeviceConfig.c +++ b/Drivers/Net/MarvellYukonDxe/DeviceConfig.c @@ -12,7 +12,6 @@ * **/ -#include <ArmPlatform.h> #include <Protocol/PciIo.h> #include <IndustryStandard/Pci.h> #include <Library/IoLib.h> diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc new file mode 100644 index 0000000..72e09fb --- /dev/null +++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.dsc @@ -0,0 +1,90 @@ +# +# Copyright (c) 2013-2016, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = MarvellYukonDxe + PLATFORM_GUID = 8391d2d4-63fc-11e6-82d5-7b6c1a2ff410 + PLATFORM_VERSION = 0.96 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/OpenPlatformPkg + SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM|AARCH64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + +[LibraryClasses] + # + # Entry point + # + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + # + # UEFI & PI + # + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + # + # Generic Modules + # + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + # + # Misc + # + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + +[LibraryClasses.common.UEFI_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent ARM compiler calls to generic intrinsic functions. + # This library provides the instrinsic functions generated by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + +[LibraryClasses.EBC] + LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf + +[PcdsFeatureFlag] + +[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.IPF] + +################################################################################################### +# +# Components Section - list of all EDK II Modules included in the build +# +################################################################################################### + +[Components] + OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf + + diff --git a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf index de1059d..cf3e870 100644 --- a/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf +++ b/Drivers/Net/MarvellYukonDxe/MarvellYukonDxe.inf @@ -56,7 +56,6 @@ DebugLib TimerLib NetLib - ArmLib DevicePathLib [Pcd] diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c index 5e7da93..139c488 100644 --- a/Drivers/Net/MarvellYukonDxe/if_msk.c +++ b/Drivers/Net/MarvellYukonDxe/if_msk.c @@ -247,7 +247,7 @@ msk_phy_readreg ( GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); for (i = 0; i < MSK_TIMEOUT; i++) { - MicroSecondDelay (1); + gBS->Stall (1); val = GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL); if ((val & GM_SMI_CT_RD_VAL) != 0) { val = GMAC_READ_2 (mSoftc, port, GM_SMI_DATA); @@ -275,7 +275,7 @@ msk_phy_writereg ( GMAC_WRITE_2 (mSoftc, port, GM_SMI_DATA, val); GMAC_WRITE_2 (mSoftc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); for (i = 0; i < MSK_TIMEOUT; i++) { - MicroSecondDelay (1); + gBS->Stall (1); if ((GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) { break; } @@ -2810,7 +2810,7 @@ msk_stop ( } else { break; } - MicroSecondDelay (1); + gBS->Stall (1); } if (i == MSK_TIMEOUT) { DEBUG ((EFI_D_NET, "Marvell Yukon: Tx BMU stop failed\n")); @@ -2856,7 +2856,7 @@ msk_stop ( if (CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RSL)) == CSR_READ_1 (mSoftc, RB_ADDR (sc_if->msk_rxq, Q_RL))) { break; } - MicroSecondDelay (1); + gBS->Stall (1); } if (i == MSK_TIMEOUT) { DEBUG ((EFI_D_NET, "Marvell Yukon: Rx BMU stop failed\n")); -- 2.7.4

9 years

[PATCH v4] Drivers/Net: Create PHY driver for Marvell platforms

by Marcin Wojtas

From: Bartosz Szczepanek <bsz(a)semihalf.com> MvPhyDxe implements support for Marvell 1512 PHYs. MARVELL_PHY_PROTOCOL is produced in order to provide Status and Initialize functions to network controller drivers. This driver requires MARVELL_MDIO_PROTOCOL to communicate with PHY device. Several PCDs were added to enable PHY ids and connection types configuration. These are described in attached documentation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bartosz Szczepanek <bsz(a)semihalf.com> Signed-off-by: Marcin Wojtas <mw(a)semihalf.com> --- Documentation/Marvell/PortingGuide/Phy.txt | 45 +++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 438 +++++++++++++++++++++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 +++++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 +++++ Platforms/Marvell/Marvell.dec | 5 + 5 files changed, 753 insertions(+) create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf diff --git a/Documentation/Marvell/PortingGuide/Phy.txt b/Documentation/Marvell/PortingGuide/Phy.txt new file mode 100644 index 0000000..69dae02 --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Phy.txt @@ -0,0 +1,45 @@ +PHY driver configuration +------------------------ +MvPhyDxe provides basic initialization and status routines for Marvell PHYs. +Currently only 1512 series PHYs are supported. Following PCDs are required: + + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + (list of values corresponding to PHY_CONNECTION enum) + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + (boolean - if true, driver waits for autonegotiation on startup) + gMarvellTokenSpaceGuid.PcdPhyDeviceIds + (list of values corresponding to MV_PHY_DEVICE_ID enum) + +PHY_CONNECTION enum type is defined as follows: + + typedef enum { +0 PHY_CONNECTION_RGMII, +1 PHY_CONNECTION_RGMII_ID, +2 PHY_CONNECTION_RGMII_TXID, +3 PHY_CONNECTION_RGMII_RXID, +4 PHY_CONNECTION_SGMII, +5 PHY_CONNECTION_RTBI, +6 PHY_CONNECTION_XAUI, +7 PHY_CONNECTION_RXAUI + } PHY_CONNECTION; + +MV_PHY_DEVICE_ID: + + typedef enum { +0 MV_PHY_DEVICE_1512, + } MV_PHY_DEVICE_ID; + +It should be extended when adding support for other PHY +models. + +Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: + + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } + +with disabled autonegotiation: + + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + +assuming, that PHY models are 1512: + + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c new file mode 100644 index 0000000..aeb6f7a --- /dev/null +++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c @@ -0,0 +1,438 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include <Protocol/DriverBinding.h> +#include <Protocol/Mdio.h> +#include <Protocol/MvPhy.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> + +#include "MvPhyDxe.h" + +#define TIMEOUT 500 + +STATIC MARVELL_MDIO_PROTOCOL *Mdio; + +STATIC MV_PHY_DEVICE MvPhyDevices[] = { + { MV_PHY_DEVICE_1512, MvPhyInit1512 }, + { 0, NULL } +}; + +EFI_STATUS +MvPhyStatus ( + IN CONST MARVELL_PHY_PROTOCOL *This, + IN PHY_DEVICE *PhyDev + ); + +EFI_STATUS +MvPhyReset ( + IN UINT32 PhyAddr + ) +{ + UINT32 Reg = 0; + INTN timeout = TIMEOUT; + + Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + Reg |= BMCR_RESET; + Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg); + + while ((Reg & BMCR_RESET) && timeout--) { + Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + gBS->Stall(1000); + } + + if (Reg & BMCR_RESET) { + DEBUG((DEBUG_ERROR, "PHY reset timed out\n")); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/* Marvell 88E1111S */ +EFI_STATUS +MvPhyM88e1111sConfig ( + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Reg; + + if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_ID) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID)) { + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + + if ((PhyDev->Connection == PHY_CONNECTION_RGMII) || + (PhyDev->Connection == PHY_CONNECTION_RGMII_ID)) { + Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_RXID) { + Reg &= ~MIIM_88E1111_TX_DELAY; + Reg |= MIIM_88E1111_RX_DELAY; + } else if (PhyDev->Connection == PHY_CONNECTION_RGMII_TXID) { + Reg &= ~MIIM_88E1111_RX_DELAY; + Reg |= MIIM_88E1111_TX_DELAY; + } + + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + + if (Reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) + Reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; + else + Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; + + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + if (PhyDev->Connection == PHY_CONNECTION_SGMII) { + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + Reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + Reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + if (PhyDev->Connection == PHY_CONNECTION_RTBI) { + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + Reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + Reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + + /* Soft reset */ + MvPhyReset(PhyDev->Addr); + + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + Reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | + MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + } + + Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg); + Reg |= (BMCR_ANENABLE | BMCR_ANRESTART); + Reg &= ~BMCR_ISOLATE; + Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg); + + /* Soft reset */ + MvPhyReset(PhyDev->Addr); + + MvPhyReset(PhyDev->Addr); + + return EFI_SUCCESS; +} + +EFI_STATUS +MvPhyParseStatus ( + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + UINT32 Speed; + + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + + if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) && + !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + INTN i = 0; + + DEBUG((DEBUG_ERROR,"MvPhyDxe: Waiting for PHY realtime link")); + while (!(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + DEBUG((DEBUG_ERROR," TIMEOUT !\n")); + PhyDev->LinkUp = FALSE; + break; + } + + if ((i++ % 1000) == 0) + DEBUG((DEBUG_ERROR, ".")); + gBS->Stall(1000); + Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + } + DEBUG((DEBUG_ERROR," done\n")); + gBS->Stall(500000); + } else { + if (Data & MIIM_88E1xxx_PHYSTAT_LINK) { + DEBUG((DEBUG_ERROR, "MvPhyDxe: link up, ")); + PhyDev->LinkUp = TRUE; + } else { + DEBUG((DEBUG_ERROR, "MvPhyDxe: link down, ")); + PhyDev->LinkUp = FALSE; + } + } + + if (Data & MIIM_88E1xxx_PHYSTAT_DUPLEX) { + DEBUG((DEBUG_ERROR, "full duplex, ")); + PhyDev->FullDuplex = TRUE; + } else { + DEBUG((DEBUG_ERROR, "half duplex, ")); + PhyDev->FullDuplex = FALSE; + } + + Speed = Data & MIIM_88E1xxx_PHYSTAT_SPEED; + + switch (Speed) { + case MIIM_88E1xxx_PHYSTAT_GBIT: + DEBUG((DEBUG_ERROR, "speed 1000\n")); + PhyDev->Speed = SPEED_1000; + break; + case MIIM_88E1xxx_PHYSTAT_100: + DEBUG((DEBUG_ERROR, "speed 100\n")); + PhyDev->Speed = SPEED_100; + break; + default: + DEBUG((DEBUG_ERROR, "speed 10\n")); + PhyDev->Speed = SPEED_10; + break; + } + + return EFI_SUCCESS; +} + +STATIC +VOID +MvPhy1512WriteBits ( + IN UINT32 PhyAddr, + IN UINT8 RegNum, + IN UINT16 Offset, + IN UINT16 Len, + IN UINT16 Data) +{ + UINT32 Reg, Mask; + + if ((Len + Offset) >= 16) + Mask = 0 - (1 << Offset); + else + Mask = (1 << (Len + Offset)) - (1 << Offset); + + Mdio->Read(Mdio, PhyAddr, RegNum, &Reg); + + Reg &= ~Mask; + Reg |= Data << Offset; + + Mdio->Write(Mdio, PhyAddr, RegNum, Reg); +} + +STATIC +EFI_STATUS +MvPhyInit1512 ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN UINT32 PhyAddr, + IN OUT PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + INTN i; + + if (PhyDev->Connection == PHY_CONNECTION_SGMII) { + /* Select page 0xff and update configuration registers according to + * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0, + * Errata Section 3.1 - needed in SGMII mode. + */ + Mdio->Write(Mdio, PhyAddr, 22, 0x00ff); + Mdio->Write(Mdio, PhyAddr, 17, 0x214B); + Mdio->Write(Mdio, PhyAddr, 16, 0x2144); + Mdio->Write(Mdio, PhyAddr, 17, 0x0C28); + Mdio->Write(Mdio, PhyAddr, 16, 0x2146); + Mdio->Write(Mdio, PhyAddr, 17, 0xB233); + Mdio->Write(Mdio, PhyAddr, 16, 0x214D); + Mdio->Write(Mdio, PhyAddr, 17, 0xCC0C); + Mdio->Write(Mdio, PhyAddr, 16, 0x2159); + + /* Reset page selection and select page 0x12 */ + Mdio->Write(Mdio, PhyAddr, 22, 0x0000); + Mdio->Write(Mdio, PhyAddr, 22, 0x0012); + + /* Write HWCFG_MODE = SGMII to Copper */ + MvPhy1512WriteBits(PhyAddr, 20, 0, 3, 1); + + /* Phy reset - necessary after changing mode */ + MvPhy1512WriteBits(PhyAddr, 20, 15, 1, 1); + + /* Reset page selection */ + Mdio->Write(Mdio, PhyAddr, 22, 0x0000); + gBS->Stall(100); + } + + MvPhyM88e1111sConfig (PhyDev); + + /* autonegotiation on startup is not always required */ + if (!PcdGetBool (PcdPhyStartupAutoneg)) + return EFI_SUCCESS; + + Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + + if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) { + + DEBUG((DEBUG_ERROR, "MvPhyDxe: Waiting for PHY auto negotiation... ")); + for (i = 0; !(Data & BMSR_ANEGCOMPLETE); i++) { + if (i > PHY_ANEG_TIMEOUT) { + DEBUG((DEBUG_ERROR, "timeout\n")); + PhyDev->LinkUp = FALSE; + return EFI_TIMEOUT; + } + + gBS->Stall(1000); /* 1 ms */ + Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + } + PhyDev->LinkUp = TRUE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); + } else { + Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + + if (Data & BMSR_LSTATUS) { + PhyDev->LinkUp = TRUE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); + } else { + PhyDev->LinkUp = FALSE; + DEBUG((DEBUG_INFO, "MvPhyDxe: link down\n")); + } + } + MvPhyParseStatus (PhyDev); + + return EFI_SUCCESS; +} + +EFI_STATUS +MvPhyInit ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN UINT32 PhyAddr, + IN PHY_CONNECTION PhyConnection, + IN OUT PHY_DEVICE **OutPhyDev + ) +{ + EFI_STATUS Status; + PHY_DEVICE *PhyDev; + UINT8 *DeviceIds; + INTN i; + + Status = gBS->LocateProtocol ( + &gMarvellMdioProtocolGuid, + NULL, + (VOID **) &Mdio + ); + if (EFI_ERROR(Status)) + return Status; + + /* perform setup common for all PHYs */ + PhyDev = AllocateZeroPool (sizeof (PHY_DEVICE)); + PhyDev->Addr = PhyAddr; + PhyDev->Connection = PhyConnection; + DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n", + PhyAddr, PhyConnection)); + *OutPhyDev = PhyDev; + + DeviceIds = PcdGetPtr (PcdPhyDeviceIds); + for (i = 0; i < PcdGetSize (PcdPhyDeviceIds); i++) { + /* find MvPhyDevices fitting entry */ + if (MvPhyDevices[i].DevId == DeviceIds[i]) { + ASSERT (MvPhyDevices[i].DevInit != NULL); + /* proceed with PHY-specific initialization */ + return MvPhyDevices[i].DevInit(Snp, PhyAddr, PhyDev); + } + } + + /* if we are here, no matching DevId was found */ + Status = EFI_INVALID_PARAMETER; + FreePool (PhyDev); + return Status; +} + +EFI_STATUS +MvPhyStatus ( + IN CONST MARVELL_PHY_PROTOCOL *This, + IN PHY_DEVICE *PhyDev + ) +{ + UINT32 Data; + + Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); + Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); + + if ((Data & BMSR_LSTATUS) == 0) { + PhyDev->LinkUp = FALSE; + } else { + PhyDev->LinkUp = TRUE; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvPhyDxeInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + MARVELL_PHY_PROTOCOL *Phy; + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + + Phy = AllocateZeroPool (sizeof (MARVELL_PHY_PROTOCOL)); + Phy->Status = MvPhyStatus; + Phy->Init = MvPhyInit; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gMarvellPhyProtocolGuid, Phy, + NULL + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to install interfaces\n")); + return Status; + } + DEBUG((DEBUG_ERROR, "Succesfully installed protocol interfaces\n")); + + return EFI_SUCCESS; +} diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h new file mode 100644 index 0000000..6bd06c5 --- /dev/null +++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h @@ -0,0 +1,194 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_PHY_DXE_H__ +#define __MV_PHY_DXE_H__ + +#define MII_BMCR 0x00 /* Basic mode control Register */ +#define MII_BMSR 0x01 /* Basic mode status Register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control Reg */ +#define MII_LPA 0x05 /* Link partner ability Reg */ +#define MII_EXPANSION 0x06 /* Expansion Register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test Reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control Register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status Register. */ +#define BMSR_ERCAP 0x0001 /* Ext-Reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +#define PHY_ANEG_TIMEOUT 4000 + +#define PHY_INTERFACE_MODE_RGMII 0 +#define PHY_INTERFACE_MODE_RGMII_ID 1 +#define PHY_INTERFACE_MODE_RGMII_RXID 2 +#define PHY_INTERFACE_MODE_RGMII_TXID 3 +#define PHY_INTERFACE_MODE_SGMII 4 +#define PHY_INTERFACE_MODE_RTBI 5 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1xxx_PHY_STATUS 0x11 +#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1xxx_PHYSTAT_100 0x4000 +#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 + +#define MIIM_88E1xxx_PHY_SCR 0x10 +#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1111 Extended PHY Specific Control Register */ +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_RX_DELAY 0x80 +#define MIIM_88E1111_TX_DELAY 0x2 + +/* 88E1111 Extended PHY Specific Status Register */ +#define MIIM_88E1111_PHY_EXT_SR 0x1b +#define MIIM_88E1111_HWCFG_MODE_MASK 0xf +#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb +#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 +#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 +#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 +#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 + +#define MIIM_88E1111_COPPER 0 +#define MIIM_88E1111_FIBER 1 + +/* 88E1118 PHY defines */ +#define MIIM_88E1118_PHY_PAGE 22 +#define MIIM_88E1118_PHY_LED_PAGE 3 + +/* 88E1121 PHY LED Control Register */ +#define MIIM_88E1121_PHY_LED_CTRL 16 +#define MIIM_88E1121_PHY_LED_PAGE 3 +#define MIIM_88E1121_PHY_LED_DEF 0x0030 + +/* 88E1121 PHY IRQ Enable/Status Register */ +#define MIIM_88E1121_PHY_IRQ_EN 18 +#define MIIM_88E1121_PHY_IRQ_STATUS 19 + +#define MIIM_88E1121_PHY_PAGE 22 + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_LED_CONTROL 24 +#define MIIM_88E1145_PHY_LED_DIRECT 0x4100 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + +#define MIIM_88E1149_PHY_PAGE 29 + +/* 88E1310 PHY defines */ +#define MIIM_88E1310_PHY_LED_CTRL 16 +#define MIIM_88E1310_PHY_IRQ_EN 18 +#define MIIM_88E1310_PHY_RGMII_CTRL 21 +#define MIIM_88E1310_PHY_PAGE 22 + +typedef enum { + MV_PHY_DEVICE_1512 +} MV_PHY_DEVICE_ID; + +typedef +EFI_STATUS +(*MV_PHY_DEVICE_INIT) ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN UINT32 PhyAddr, + IN OUT PHY_DEVICE *PhyDev + ); + +typedef struct { + MV_PHY_DEVICE_ID DevId; + MV_PHY_DEVICE_INIT DevInit; +} MV_PHY_DEVICE; + +STATIC +EFI_STATUS +MvPhyInit1512 ( + IN CONST MARVELL_PHY_PROTOCOL *Snp, + IN UINT32 PhyAddr, + IN OUT PHY_DEVICE *PhyDev + ); + +#endif diff --git a/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf new file mode 100644 index 0000000..713eada --- /dev/null +++ b/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf @@ -0,0 +1,71 @@ +# Copyright (C) 2016 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MvPhyDxe + FILE_GUID = 5aac3843-d8d4-40ba-ae07-38967138509c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MvPhyDxeInitialise + +[Sources.common] + MvPhyDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gMarvellMdioProtocolGuid + gMarvellPhyProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + gMarvellTokenSpaceGuid.PcdPhyDeviceIds + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + +[Depex] + TRUE diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 9c53b8c..73102ed 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -181,6 +181,11 @@ #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043 +#PHY + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0 }|VOID*|0x3000044 + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0 }|VOID*|0x3000095 + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070 + [Protocols] gMarvellEepromProtocolGuid = { 0xcd728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} gMarvellMdioProtocolGuid = { 0x0d728a1f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} -- 1.8.3.1

9 years

Platform independent driver

by Daniil Egranov

Hi, I am looking at proper implementation for a driver which does not depend on a platform but can be built for any supported architecture like EBC, AARCH64, etc. That means the driver can be built separately from the platform specific dsc but still be able to use proper platform implemented interface functions once it's loaded (ex. from UEFI Shell). As an example of a platform specific call: for (i = 0; i < MSK_TIMEOUT; i++) { MicroSecondDelay (1); val = GMAC_READ_2 (mSoftc, port, GM_SMI_CTRL); if ((val & GM_SMI_CT_RD_VAL) != 0) { val = GMAC_READ_2 (mSoftc, port, GM_SMI_DATA); break; } } If the driver is using MicroSecondDelay() (code above) and is built as part of the Juno platform dsc, the MicroSecondDelay() will be linked to its implementation in ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c. If the driver has not been built as part of any platform, MicroSecondDelay() will be linked to MdePkg/Library/BaseTimerLibNullTemplate/TimerLibNull.c implementation. So if the driver is built as platform independent (or architecture independent in case of EBC) and included in the controller's option ROM (or shipped as a file), it will fail as it will not be able to call correct platform interface function. This means the driver should do runtime (load time) bindings to the platform interface functions to be a "platform independent". Does the EDK2 provide a way to do such dynamic bindings? Thanks, Daniil

9 years

[PATCH v3 0/8] Armada 7040 serdes support and network preparation

by Marcin Wojtas

Hi, Here is the third version of a patchset adding network preparation support for Armada 7040 SoC, i.e. SerDes, MDIO and PHY libraries. All comments from v2 are included, more details in changelog below. The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v2 -> v3 *ComPhyLib: - Move all calls to GetComPhyPcd macro to separate function, because of its embroiled structure - Clean-up *MDIO driver - Rename folder Drivers/Net/MdioDxe -> Drivers/Net/MvMdioDxe * PHY driver - Replace meaningless comments with more proper one - Unify values format written to the phy during intialization v1 -> v2 * ComPhyLib - Remove obsolete support for Z1 chip - delete SerDes init sequence, which isn't longer executed - Break up long functions with lanes' power up sequence into smaller (atomic) ones - Update documenatation - Minor changes in namings * MDIO and PHY Library - Change MdioRead interface (use better approach of error handling) - Renaming and sorting - Improve commit messages * Others - Rebase on top of 07/30 linaro-opp master branch Bartosz Szczepanek (6): Platforms/Marvell: Include common network modules on Armada SoC's Platforms/Marvell: Add MARVELL_MDIO_PROTOCOL Platforms/Marvell: Enable MDIO driver on Armada70x0 platform Platforms/Marvell: Add MARVELL_PHY_PROTOCOL Drivers/Net: Create PHY driver for Marvell platforms Platforms/Marvell: Enable PHY driver on Armada70x0 platform Jan Dąbroś (2): Platforms/Marvell: Create ComPhyLib Platforms/Marvell: Enable ComPhy Lib for Armada70x0 platform Documentation/Marvell/PortingGuide/ComPhy.txt | 85 ++ Documentation/Marvell/PortingGuide/Mdio.txt | 7 + Documentation/Marvell/PortingGuide/Phy.txt | 45 + Drivers/Net/MvMdioDxe/MvMdioDxe.c | 237 +++++ Drivers/Net/MvMdioDxe/MvMdioDxe.h | 57 ++ Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 69 ++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 432 ++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 ++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 20 +- Platforms/Marvell/Armada/Armada70x0.dsc | 20 + Platforms/Marvell/Armada/Armada70x0.fdf | 14 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 4 +- .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/MvComPhyLib.h | 43 + Platforms/Marvell/Include/Protocol/Mdio.h | 66 ++ Platforms/Marvell/Include/Protocol/MvPhy.h | 103 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 1047 ++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 288 ++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 452 +++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 109 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 +++ Platforms/Marvell/Marvell.dec | 60 ++ 23 files changed, 3553 insertions(+), 3 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Documentation/Marvell/PortingGuide/Mdio.txt create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/MvMdioDxe/MvMdioDxe.c create mode 100644 Drivers/Net/MvMdioDxe/MvMdioDxe.h create mode 100644 Drivers/Net/MvMdioDxe/MvMdioDxe.inf create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf create mode 100644 Platforms/Marvell/Include/Library/MvComPhyLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Mdio.h create mode 100644 Platforms/Marvell/Include/Protocol/MvPhy.h create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c -- 1.8.3.1

9 years

SATA AHCI issue

by Shaveta Leekha

Hi, I have been working on support for AHCI controller for my ARMv8 platform. For that I have integrated my PciEmulation code and SataControllerDxe driver code with MdeModulePkg/Bus/Ata. But facing one issue, this is same issue reported by Jan Dabros(in To list) sometime back. Setting PxCMD.FRE bit of command register doesn't cause PxCMD.FR to be set to '1' even after "500msec" timeout. (As per AHCI spec 1.3 : When PxCMD.FRE is set, it causes PxCMD.FR to be set to '1' ) Is it correct to just comment out following code part from "MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c" file, "AhciModeInitialization" function: As Initialization timeouts is occurring in below part of code: // // Enable FIS Receive DMA engine for the first D2H FIS. // Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD; AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); Status = AhciWaitMmioSet ( PciIo, Offset, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR, EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT ); if (EFI_ERROR (Status)) { continue; } And if above code is commented out, then SATA stack works completely fine. What can be the problem? Thank you in advance for your time! Best regards, Shaveta

9 years

[linaro-uefi] Two write to EOIR in a single interrupt

by Heyi Guo

Hi folks, We can see that in a single timer interrupt, there will be two writes to EOIR, one in timer interrupt handler, the other in GIC IRQ handler. The question is: does two writes to EOIR have any side effect? From GIC specification (ARM IHI 0069B (ID121715)), we can see below text about writing EOIR (page 205): A write to this register must correspond to the most recent valid read from an Interrupt Acknowledge Register for which there has not been a priority drop and that this identifier was read from ICC_IAR1_EL1 while operating in the same Security state as that in which the write occurs, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid interrupt ID, that is not a special INTID. For GICv2, we can also see below text about EOIR: For nested interrupts, the order of writes to this register must be the reverse of the order of interrupt acknowledgement. Behavior is UNPREDICTABLE if: • This ordering constraint is not maintained. *• The value written to this register does not match an active interrupt, or the ID of a spurious interrupt. * • The value written to this register does not match the last valid interrupt value read from GICC_IAR. When we issue the 1st EOIR, the interrupt will be deactivated, so it is not in active state anymore for the 2nd write of EOIR. Could anyone help to confirm whether it is OK to keep the 2nd write of EOIR? And how to explain the above paragraphs from GIC specification? Thanks and regards. Heyi

9 years

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