Linaro-uefi

linaro-uefi@lists.linaro.org

811 discussions

[PATCH v2 0/8] Armada 7040 serdes support and network preparation

by Marcin Wojtas

Hi, Here is the second version of a patchset adding network preparation support for Armada 7040 SoC, i.e. SerDes, MDIO and PHY libraries. All comments from v1 are included, more details in changelog below. The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Best regards, Marcin Changelog: v1 -> v2 * ComPhyLib - Remove obsolete support for Z1 chip - delete SerDes init sequence, which isn't longer executed - Break up long functions with lanes' power up sequence into smaller (atomic) ones - Update documenatation - Minor changes in namings * MDIO and PHY Library - Change MdioRead interface (use better approach of error handling) - Renaming and sorting - Improve commit messages * Others - Rebase on top of 07/30 linaro-opp master branch Bartosz Szczepanek (6): Platforms/Marvell: Include common network modules on Armada SoC's Platforms/Marvell: Add MARVELL_MDIO_PROTOCOL Platforms/Marvell: Enable MDIO driver on Armada70x0 platform Platforms/Marvell: Add MARVELL_PHY_PROTOCOL Drivers/Net: Create PHY driver for Marvell platforms Platforms/Marvell: Enable PHY driver on Armada70x0 platform Jan Dąbroś (2): Platforms/Marvell: Create ComPhyLib Platforms/Marvell: Enable ComPhy Lib for Armada70x0 platform Documentation/Marvell/PortingGuide/ComPhy.txt | 85 ++ Documentation/Marvell/PortingGuide/Mdio.txt | 7 + Documentation/Marvell/PortingGuide/Phy.txt | 45 + Drivers/Net/MdioDxe/MvMdioDxe.c | 237 +++++ Drivers/Net/MdioDxe/MvMdioDxe.h | 57 ++ Drivers/Net/MdioDxe/MvMdioDxe.inf | 69 ++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 429 ++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 ++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 20 +- Platforms/Marvell/Armada/Armada70x0.dsc | 20 + Platforms/Marvell/Armada/Armada70x0.fdf | 14 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 4 +- .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/MvComPhyLib.h | 43 + Platforms/Marvell/Include/Protocol/Mdio.h | 66 ++ Platforms/Marvell/Include/Protocol/MvPhy.h | 103 ++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 1023 ++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 275 ++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 452 +++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 109 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 +++ Platforms/Marvell/Marvell.dec | 60 ++ 23 files changed, 3513 insertions(+), 3 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Documentation/Marvell/PortingGuide/Mdio.txt create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.c create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.h create mode 100644 Drivers/Net/MdioDxe/MvMdioDxe.inf create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf create mode 100644 Platforms/Marvell/Include/Library/MvComPhyLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Mdio.h create mode 100644 Platforms/Marvell/Include/Protocol/MvPhy.h create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c -- 1.8.3.1

8 years, 4 months

[PATCH] Platforms/ARM/Juno: limit ACPI support to v5.0 and higher

by Sudeep Holla

The ACPI spec predates the AARCH64 architecture by 5 versions, so there is no point in supporting anything below v5.0. So set the PCD that controls the ACPI table generation to the appropriate value. Based on the commit e0692789058e ("ArmVirtPkg/ArmVirtQemu: limit ACPI support to v5.0 and higher") in the upstream TianoCore by Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheu...(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 45d9950decba..2e9ccfbad396 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -174,6 +174,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + [PcdsPatchableInModule] # Console Resolution (Full HD) gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920 -- 2.7.4

8 years, 4 months

[PATCH] Platforms/ARM/Juno: Add support for ACPI 6.0 LPI(Low Power Idle) states

by Sudeep Holla

ACPI 6.0 introduced LPI(Low Power Idle) states that provides an alternate method to describe processor idle states. LPI extensions leverages the processor container device(again introduced in ACPI 6.0) allowing to express which parts of the system are affected by a given LPI state. It defines the local power states for each node in a hierarchical processor topology. The OSPM can use _LPI object to select a local power state for each level of processor hierarchy in the system. This patch adds LPI support on Juno. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla(a)arm.com> --- Platforms/ARM/Juno/AcpiTables/Dsdt.asl | 232 ++++++++++++++++++++++++++++++--- 1 file changed, 213 insertions(+), 19 deletions(-) Hi Lief, The support in the kernel is now added(latest mainline as of today) and is enabled in defconfig. It's easy to test, just examine the sysfs entries: /sys/devices/system/cpu/cpu*/cpuidle/state*/desc - Describes the cpuidle state /sys/devices/system/cpu/cpu*/cpuidle/state*/{usage,time} - Should keep ticking with time signifying that the idle states are entered and exited correctly Regards, Sudeep diff --git a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl index c324ded471f2..07e32bae21f8 100644 --- a/Platforms/ARM/Juno/AcpiTables/Dsdt.asl +++ b/Platforms/ARM/Juno/AcpiTables/Dsdt.asl @@ -19,29 +19,223 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O // // A57x2-A53x4 Processor declaration // - Device(CPU0) { // A53-0: Cluster 1, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 0) + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { + If (!(Arg1 == One)) { + STS0 &= ~0x1F + STS0 |= 0x0A + } Else { + If ((CAP0 & 0x100)) { + CAP0 &= ~0x100 /* No support for OS Initiated LPI */ + STS0 &= ~0x1F + STS0 |= 0x12 + } + } + } Else { + STS0 &= ~0x1F + STS0 |= 0x06 + } + Return (Arg3) } - Device(CPU1) { // A53-1: Cluster 1, Cpu 1 - Name(_HID, "ACPI0007") + Device (CLU0) { // Cluster0 state + Name(_HID, "ACPI0010") Name(_UID, 1) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU0) { // A57-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU1) { // A57-1: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } - Device(CPU2) { // A53-2: Cluster 1, Cpu 2 - Name(_HID, "ACPI0007") + Device (CLU1) { // Cluster1 state + Name(_HID, "ACPI0010") Name(_UID, 2) - } - Device(CPU3) { // A53-3: Cluster 1, Cpu 3 - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { // A57-0: Cluster 0, Cpu 0 - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { // A57-1: Cluster 0, Cpu 1 - Name(_HID, "ACPI0007") - Name(_UID, 5) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU2) { // A53-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU3) { // A53-1: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU4) { // A53-2: Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU5) { // A53-3: Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } } // -- 2.7.4

8 years, 4 months

[PATCH] OpenPlatformPkg/MarvellYukonDxe: Fix for RELEASE build

by Daniil Egranov

Fixed compilation warning treated as error during the RELEASE build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov(a)arm.com> --- Drivers/Net/MarvellYukonDxe/if_msk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Drivers/Net/MarvellYukonDxe/if_msk.c b/Drivers/Net/MarvellYukonDxe/if_msk.c index 5e7da93..8436641 100644 --- a/Drivers/Net/MarvellYukonDxe/if_msk.c +++ b/Drivers/Net/MarvellYukonDxe/if_msk.c @@ -1138,6 +1138,7 @@ mskc_attach ( UINT32 MacAddrH; EFI_STATUS Status; struct msk_if_softc *ScIf; + const CHAR8 *ModelName; mPciIo = PciIo; mSoftc = AllocateZeroPool (sizeof (struct msk_softc)); @@ -1213,8 +1214,10 @@ mskc_attach ( Status = EFI_DEVICE_ERROR; goto RESTORE_PCI_ATTRIBS; } + + ModelName = model_name[mSoftc->msk_hw_id - CHIP_ID_YUKON_XL]; DEBUG ((EFI_D_NET, "Marvell Yukon: Marvell Technology Group Ltd. %a Id:0x%02x Rev:0x%02x\n", - model_name[mSoftc->msk_hw_id - CHIP_ID_YUKON_XL], mSoftc->msk_hw_id, mSoftc->msk_hw_rev)); + ModelName, mSoftc->msk_hw_id, mSoftc->msk_hw_rev)); mSoftc->msk_process_limit = MSK_PROC_DEFAULT; mSoftc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; -- 2.7.4

8 years, 4 months

[PATCH 0/8] Armada 7040 serdes support and network preparation

by Marcin Wojtas

Hi, Since basic support of Armada 7040 has been integrated to the tree, here is another part of the platform. Below commits comprise three parts: * ComPhy library - SerDes configuration and multiplexing * MDIO library * PHY library Altogether they are needed for enabling network on Armada 7040 (driver not included in this patchset). The patches are also available in the public github tree: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp… Any comments or remarks would be welcome. Bartosz Szczepanek (6): Platforms/Marvell: Include common network modules on Armada SoC's Platforms/Marvell: Add MARVELL_MDIO_PROTOCOL Platforms/Marvell: Enable MDIO driver on Armada70x0 platform Platforms/Marvell: Add MARVELL_PHY_PROTOCOL Drivers/Net: Create PHY driver for Marvell platforms Platforms/Marvell: Enable PHY driver on Armada70x0 platform Jan Dąbroś (2): Platforms/Marvell: Create ComPhyLib Platforms/Marvell: Enable ComPhy Lib for Armada70x0 platform Documentation/Marvell/PortingGuide/ComPhy.txt | 82 +++ Documentation/Marvell/PortingGuide/Mdio.txt | 7 + Documentation/Marvell/PortingGuide/Phy.txt | 45 ++ Drivers/Net/MdioDxe/MdioDxe.c | 235 ++++++ Drivers/Net/MdioDxe/MdioDxe.h | 57 ++ Drivers/Net/MdioDxe/MdioDxe.inf | 68 ++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 439 +++++++++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 194 +++++ Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 71 ++ Platforms/Marvell/Armada/Armada.dsc.inc | 20 +- Platforms/Marvell/Armada/Armada70x0.dsc | 21 + Platforms/Marvell/Armada/Armada70x0.fdf | 14 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 2 + .../Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 1 + Platforms/Marvell/Include/Library/ComPhyLib.h | 43 ++ Platforms/Marvell/Include/Protocol/Mdio.h | 65 ++ Platforms/Marvell/Include/Protocol/Phy.h | 103 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c | 290 ++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c | 812 +++++++++++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c | 277 +++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h | 457 ++++++++++++ Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf | 111 +++ Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c | 132 ++++ Platforms/Marvell/Marvell.dec | 61 ++ 24 files changed, 3606 insertions(+), 1 deletion(-) create mode 100644 Documentation/Marvell/PortingGuide/ComPhy.txt create mode 100644 Documentation/Marvell/PortingGuide/Mdio.txt create mode 100644 Documentation/Marvell/PortingGuide/Phy.txt create mode 100644 Drivers/Net/MdioDxe/MdioDxe.c create mode 100644 Drivers/Net/MdioDxe/MdioDxe.h create mode 100644 Drivers/Net/MdioDxe/MdioDxe.inf create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h create mode 100644 Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf create mode 100644 Platforms/Marvell/Include/Library/ComPhyLib.h create mode 100644 Platforms/Marvell/Include/Protocol/Mdio.h create mode 100644 Platforms/Marvell/Include/Protocol/Phy.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyAp806.c create mode 100755 Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.c create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyLib.inf create mode 100644 Platforms/Marvell/Library/ComPhyLib/ComPhyMux.c -- 1.8.3.1

8 years, 4 months

[PATCH v5] Platforms/ARM/Juno: Create SMBIOS/DMI data for Juno

by Jeremy Linton

SMBIOS data is consumed by a wide range of enterprise applications. Fill in the basic requirements of the SMBIOS specification by hardcoding the minimum required structures and data using Juno information. Only the juno revision, memory ranges and CPU types are dynamic. Add the resulting Juno SmbiosPlatformDxe and MdeModulePkg/SmbiosDxe to the build and firmware image. With these changes, the EFI BDS, EFI shell, and Linux dmidecode command return useful information. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 12 + Platforms/ARM/Juno/ArmJuno.fdf | 6 + .../ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 865 +++++++++++++++++++++ .../Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 68 ++ 4 files changed, 951 insertions(+) create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 84c2441..c51d8f2 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -178,6 +178,12 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + # + # SMBIOS entry point version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + [PcdsPatchableInModule] # Console Resolution (Full HD) gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920 @@ -312,6 +318,12 @@ } # + # SMBIOS/DMI + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # # Bds # MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf index a01db20..04d9a3c 100644 --- a/Platforms/ARM/Juno/ArmJuno.fdf +++ b/Platforms/ARM/Juno/ArmJuno.fdf @@ -202,6 +202,12 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf # + # SMBIOS/DMI + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # # Bds # INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c new file mode 100644 index 0000000..fe5498e --- /dev/null +++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -0,0 +1,865 @@ +/** @file + This driver installs SMBIOS information for ARM Juno platforms + + Copyright (c) 2015, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <ArmPlatform.h> +#include <IndustryStandard/SmBios.h> +#include <Library/ArmLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <PiDxe.h> +#include <Protocol/Smbios.h> + +#define TYPE0_STRINGS \ + "EFI Development Kit II / ARM LTD\0" /* Vendor */ \ + "EDK II\0" /* BiosVersion */ \ + __DATE__"\0" /* BiosReleaseDate */ + +#define TYPE1_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "ARM Juno Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + " \0" /* 20 character buffer */ + +#define TYPE2_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "ARM Juno Development Platform\0" /* Product Name */ \ + "R0\0" /* Version */ \ + "Serial Not Set\0" /* Serial */ \ + "Base of Chassis\0" /* board location */ \ + "R1\0" /* Version */ \ + "R2\0" /* Version */ + +#define TYPE3_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "None\0" /* Version */ \ + "Serial Not Set\0" /* Serial */ + +#define TYPE4_STRINGS \ + "BGA-1156\0" /* socket type */ \ + "ARM LTD\0" /* manufactuer */ \ + "Cortex-A57\0" /* processor 1 description */ \ + "Cortex-A53\0" /* processor 2 description */ \ + "Cortex-A72\0" /* processor 2 description */ \ + "0xd03\0" /* A53 part number */ \ + "0xd07\0" /* A57 part number */ \ + "0xd08\0" /* A72 part number */ + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ + +#define TYPE9_STRINGS \ + "PCIE_SLOT0\0" /* Slot0 */ \ + "PCIE_SLOT1\0" /* Slot1 */ \ + "PCIE_SLOT2\0" /* Slot2 */ \ + "PCIE_SLOT3\0" /* Slot3 */ + +#define TYPE16_STRINGS \ + "\0" /* nothing */ + +#define TYPE17_STRINGS \ + "RIGHT SIDE\0" /* location */ \ + "BANK 0\0" /* bank description */ + +#define TYPE19_STRINGS \ + "\0" /* nothing */ + +#define TYPE32_STRINGS \ + "\0" /* nothing */ + + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE0 Base; + INT8 Strings[sizeof(TYPE0_STRINGS)]; +} ARM_TYPE0; + +typedef struct { + SMBIOS_TABLE_TYPE1 Base; + UINT8 Strings[sizeof(TYPE1_STRINGS)]; +} ARM_TYPE1; + +typedef struct { + SMBIOS_TABLE_TYPE2 Base; + UINT8 Strings[sizeof(TYPE2_STRINGS)]; +} ARM_TYPE2; + +typedef struct { + SMBIOS_TABLE_TYPE3 Base; + UINT8 Strings[sizeof(TYPE3_STRINGS)]; +} ARM_TYPE3; + +typedef struct { + SMBIOS_TABLE_TYPE4 Base; + UINT8 Strings[sizeof(TYPE4_STRINGS)]; +} ARM_TYPE4; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof(TYPE7_STRINGS)]; +} ARM_TYPE7; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof(TYPE9_STRINGS)]; +} ARM_TYPE9; + +typedef struct { + SMBIOS_TABLE_TYPE16 Base; + UINT8 Strings[sizeof(TYPE16_STRINGS)]; +} ARM_TYPE16; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof(TYPE17_STRINGS)]; +} ARM_TYPE17; + +typedef struct { + SMBIOS_TABLE_TYPE19 Base; + UINT8 Strings[sizeof(TYPE19_STRINGS)]; +} ARM_TYPE19; + +typedef struct { + SMBIOS_TABLE_TYPE32 Base; + UINT8 Strings[sizeof(TYPE32_STRINGS)]; +} ARM_TYPE32; + +// SMBIOS tables often reference each other using +// fixed constants, define a list of these constants +// for our hardcoded tables +enum SMBIOS_REFRENCE_HANDLES { + SMBIOS_HANDLE_A57_L1I = 0x1000, + SMBIOS_HANDLE_A57_L1D, + SMBIOS_HANDLE_A57_L2, + SMBIOS_HANDLE_A53_L1I, + SMBIOS_HANDLE_A53_L1D, + SMBIOS_HANDLE_A53_L2, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_A72_CLUSTER, + SMBIOS_HANDLE_A57_CLUSTER, + SMBIOS_HANDLE_A53_CLUSTER, + SMBIOS_HANDLE_MEMORY, + SMBIOS_HANDLE_DIMM +}; + +#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure + +#pragma pack() + +// BIOS information (section 7.1) +STATIC ARM_TYPE0 mArmDefaultType0 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // SMBIOS_TABLE_STRING Vendor + 2, // SMBIOS_TABLE_STRING BiosVersion + 0xE800,// UINT16 BiosSegment + 3, // SMBIOS_TABLE_STRING BiosReleaseDate + 0, // UINT8 BiosSize + { + 0,0,0,0,0,0, + 1, //PCI supported + 0, + 1, //PNP supported + 0, + 1, //BIOS upgradable + 0, 0, 0, + 1, //Boot from CD + 1, //selectable boot + }, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics + { // BIOSCharacteristicsExtensionBytes[2] + 0x3, + 0xC, + }, + 0, // UINT8 SystemBiosMajorRelease + 0, // UINT8 SystemBiosMinorRelease + 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease + 0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease + }, + // Text strings (unformatted area) + TYPE0_STRINGS +}; + +// System information (section 7.2) +STATIC CONST ARM_TYPE1 mArmDefaultType1 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, + sizeof(SMBIOS_TABLE_TYPE1), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //Manufacturer + 2, //Product Name + 3, //Version + 4, //Serial + { 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }}, //UUID + 6, //Wakeup type + 0, //SKU + 0, //Family + }, + // Text strings (unformatted) + TYPE1_STRINGS +}; + +// Baseboard (section 7.3) +STATIC ARM_TYPE2 mArmDefaultType2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length + SMBIOS_HANDLE_MOTHERBOARD, + }, + 1, //Manufacturer + 2, //Product Name + 3, //Version + 4, //Serial + 0, //Asset tag + {1}, //motherboard, not replaceable + 5, //location of board + SMBIOS_HANDLE_CHASSIS, + BaseBoardTypeMotherBoard, + 1, + {SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY}, + }, + TYPE2_STRINGS +}; + +// Enclosure +STATIC CONST ARM_TYPE3 mArmDefaultType3 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length + SMBIOS_HANDLE_CHASSIS, + }, + 1, //Manufacturer + 4, //enclosure type (low profile desktop) + 2, //version + 3, //serial + 0, //asset tag + ChassisStateUnknown, //boot chassis state + ChassisStateSafe, //power supply state + ChassisStateSafe, //thermal state + ChassisSecurityStatusNone, //security state + {0,0,0,0,}, //OEM defined + 1, //1U height + 1, //number of power cords + 0, //no contained elements + }, + TYPE3_STRINGS +}; + +// Processor +STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A72_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 5, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 1200, //max speed + 1200, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A57_L1I, //l1 cache handle + SMBIOS_HANDLE_A57_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 8, //part number + 2, //core count in socket + 2, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A57_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 3, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 1200, //max speed + 1200, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A57_L1I, //l1 cache handle + SMBIOS_HANDLE_A57_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 7, //part number + 2, //core count in socket + 2, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A53_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 4, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 650, //max speed + 650, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A53_L1I, //l1 cache handle + SMBIOS_HANDLE_A53_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 6, //part number + 4, //core count in socket + 4, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +// Cache +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L1I, + }, + 1, + 0x380, //L1 enabled, unknown WB + 48, //48k i cache max + 48, //48k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorParity, //parity checking + CacheTypeInstruction, //instruction cache + CacheAssociativityOther, //three way + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L1I, + }, + 1, + 0x380, //L1 enabled, unknown WB + 32, //32k i cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorParity, //parity checking + CacheTypeInstruction, //instruction cache + CacheAssociativity2Way, //two way + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L1D, + }, + 2, + 0x180, //L1 enabled, WB + 32, //32k d cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeData, //instruction cache + CacheAssociativity2Way, //two way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L1D, + }, + 2, + 0x180, //L1 enabled, WB + 32, //32k d cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeData, //instruction cache + CacheAssociativity4Way, //four way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L2, + }, + 3, + 0x181, //L2 enabled, WB + 2048, //2M d cache max + 2048, //2M installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeUnified, //instruction cache + CacheAssociativity16Way, //16 way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L2, + }, + 3, + 0x181, //L2 enabled, WB + 1024, //1M D cache max + 1024, //1M installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeUnified, //instruction cache + CacheAssociativity16Way, //16 way associative + }, + TYPE7_STRINGS +}; + +// Slots +STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X4, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, //unknown + {1,0,1}, //PME and SMBUS + 0, + 2, + 1, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X4, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 2, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X8, + SlotDataBusWidth4X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 3, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X16, + SlotDataBusWidth4X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 0xc, + }, + TYPE9_STRINGS +}; + +// Memory array +STATIC CONST ARM_TYPE16 mArmDefaultType16 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length + SMBIOS_HANDLE_MEMORY, + }, + MemoryArrayLocationSystemBoard, //on motherboard + MemoryArrayUseSystemMemory, //system RAM + MemoryErrorCorrectionNone, //Juno doesn't have ECC RAM + 0x800000, //8GB + 0xFFFE, //No error information structure + 0x1, //soldered memory + }, + TYPE16_STRINGS +}; + +// Memory device +STATIC CONST ARM_TYPE17 mArmDefaultType17 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM, + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this would be 72) + 64, //data width of this device (64-bits) + 0x2000, //8GB + 0x0B, //row of chips + 0, //not part of a set + 1, //right side of board + 2, //bank 0 +// MemoryTypeLpddr3, //LP DDR3, isn't defined yet + MemoryTypeDdr3, //LP DDR3 + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered + 1600, //1600Mhz DDR + 0, //varies between diffrent production runs + 0, //serial + 0, //asset tag + 0, //part number + 0, //rank + }, + TYPE17_STRINGS +}; + +// Memory array mapped address, this structure +// is overridden by InstallMemoryStructure +STATIC CONST ARM_TYPE19 mArmDefaultType19 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 0xFFFFFFFF, //invalid, look at extended addr field + 0xFFFFFFFF, + SMBIOS_HANDLE_DIMM, //handle + 1, + 0x080000000, //starting addr of first 2GB + 0x100000000, //ending addr of first 2GB + }, + TYPE19_STRINGS +}; + +// System boot info +STATIC CONST ARM_TYPE32 mArmDefaultType32 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + {0,0,0,0,0,0}, //reserved + BootInformationStatusNoError, + }, + TYPE32_STRINGS +}; + +STATIC CONST VOID *DefaultCommonTables[]= +{ + &mArmDefaultType0, + &mArmDefaultType1, + &mArmDefaultType2, + &mArmDefaultType3, + &mArmDefaultType7_a53_l1i, + &mArmDefaultType7_a53_l1d, + &mArmDefaultType7_a53_l2, + &mArmDefaultType4_a53, + &mArmDefaultType9_0, + &mArmDefaultType9_1, + &mArmDefaultType9_2, + &mArmDefaultType9_3, + &mArmDefaultType16, + &mArmDefaultType17, +// &mArmDefaultType19, //memory range type 19 dynamically generated + &mArmDefaultType32, + NULL +}; + +STATIC CONST VOID *DefaultTablesR0R1[]= +{ + &mArmDefaultType7_a57_l1i, + &mArmDefaultType7_a57_l1d, + &mArmDefaultType7_a57_l2, + &mArmDefaultType4_a57, + NULL +}; + +STATIC CONST VOID *DefaultTablesR2[]= +{ + &mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57 + &mArmDefaultType7_a57_l1d, + &mArmDefaultType7_a57_l2, + &mArmDefaultType4_a72, + NULL +}; + + +/** + Installs a memory descriptor (type19) for the given address range + + @param Smbios SMBIOS protocol + +**/ +EFI_STATUS +InstallMemoryStructure ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINT64 StartingAddress, + IN UINT64 RegionLength + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + ARM_TYPE19 MemoryDescriptor; + EFI_STATUS Status = EFI_SUCCESS; + + CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19)); + + MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress; + MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength; + SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle; + + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor + ); + return Status; +} + +/** + Install a whole table worth of structructures + + @parm +**/ +EFI_STATUS +InstallStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN CONST VOID *DefaultTables[] + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_SMBIOS_HANDLE SmbiosHandle; + + int TableEntry; + for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++) + { + SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry] + ); + if (EFI_ERROR(Status)) + break; + } + return Status; +} + + +/** + Install all structures from the DefaultTables structure + + @param Smbios SMBIOS protocol + +**/ +EFI_STATUS +InstallAllStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 JunoRevision; + VOID *ExtraTables = DefaultTablesR0R1; + + GetJunoRevision(JunoRevision); + + // Fixup some table values + mArmDefaultType0.Base.SystemBiosMajorRelease = (PcdGet32 ( PcdFirmwareRevision ) >> 16) & 0xFF; + mArmDefaultType0.Base.SystemBiosMinorRelease = PcdGet32 ( PcdFirmwareRevision ) & 0xFF; + if ( JunoRevision == JUNO_REVISION_R1 ) + { + mArmDefaultType2.Base.Version = 6; + } + else if ( JunoRevision == JUNO_REVISION_R2 ) + { + mArmDefaultType2.Base.Version = 7; + ExtraTables=DefaultTablesR2; + } + + // + // Add all Juno table entries + // + Status=InstallStructures (Smbios,DefaultCommonTables); + ASSERT_EFI_ERROR (Status); + + Status=InstallStructures (Smbios,ExtraTables); + ASSERT_EFI_ERROR (Status); + + // Generate memory descriptors for the two memory ranges we know about + Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize)); + ASSERT_EFI_ERROR (Status); + Status = InstallMemoryStructure ( Smbios, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Installs SMBIOS information for ARM platforms + + @param ImageHandle Module's image handle + @param SystemTable Pointer of EFI_SYSTEM_TABLE + + @retval EFI_SUCCESS Smbios data successfully installed + @retval Other Smbios data was not installed + +**/ +EFI_STATUS +EFIAPI +SmbiosTablePublishEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Find the SMBIOS protocol + // + Status = gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID**)&Smbios + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = InstallAllStructures (Smbios); + + return Status; +} diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf new file mode 100644 index 0000000..457e1ff --- /dev/null +++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -0,0 +1,68 @@ +## @file +# This driver installs SMBIOS information for ArmJuno +# +# Copyright (c) 2011, Bei Guan <gbtju85(a)gmail.com> +# Copyright (c) 2011, Intel Corporation. All rights reserved. +# Copyright (c) 2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmbiosPlatformDxe + FILE_GUID = 4110465d-5ff3-4f4b-b580-24ed0d06747a + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = SmbiosTablePublishEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + SmbiosPlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseMemoryLib + BaseLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + gEfiGlobalVariableGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid -- 2.5.5

8 years, 5 months

[PATCH 1/9] D02/D03: ACPI/Hns: add media-type property for hns

by Heyi Guo

From: Kejian Yan <yankejian(a)huawei.com> It is PORT_TP type if the service port is GE mode. It is wrong to judge the port type by using if it is service port. Adding the media type to know port type. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kejian Yan <yankejian(a)huawei.com> Signed-off-by: Heyi Guo <heyi.guo(a)linaro.org> --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl | 4 ++++ Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl index aa83489..b62ee45 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/D03Hns.asl @@ -466,6 +466,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -476,6 +477,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -489,6 +491,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -502,6 +505,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl index 5945fc3..2b08a1f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -439,6 +439,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 0}, + Package () {"media-type", "fiber"}, } }) } @@ -449,6 +450,7 @@ Scope(_SB) ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () {"reg", 1}, + Package () {"media-type", "fiber"}, } }) } @@ -462,6 +464,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 0}, Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } @@ -475,6 +478,7 @@ Scope(_SB) Package () {"phy-mode", "sgmii"}, Package () {"phy-addr", 1}, Package () {"mdio-node", Package (){\_SB.MDIO}}, + Package () {"media-type", "copper"}, } }) } -- 2.7.0

8 years, 5 months

[PATCH v4 0/6] ArmJuno: Add SMBIOS/DMI support

by Jeremy Linton

v3-v4: Rebase/Split patch for newer edk2/OpenPlatformPkg v2-v3: Add JunoR2 support, replace CPU MIDR code with board revision detection v1->v2: General cleanups, move juno revision macro info platform.h SMBIOS data is consumed by a wide range of enterprise applications. Fill in the basic requirements of the SMBIOS specification by hardcoding the minimum required structures and data using Juno information. With this change both the EFI shell, BDS and linux dmidecode commands return useful information. This patch set is actually against both edk2 and OpenPlatformPkg. The first three patches apply against edk2, the last three against OpenPlatformPkg. Jeremy Linton (3): ArmPlatformPkg: Add A72 CPU type Code to detect what juno revision we are running on. Convert ArmJunoDxe to use common juno revision code Jeremy Linton (3): Platforms/ARM/Juno: Create SMBIOS/DMI data for Juno Platforms/ARM/Juno: Add the module build information Platforms/ARM/Juno: Add the SMBIOS/DMI module to the Juno Platform ArmPkg/Include/Chipset/AArch64.h | 1 + .../ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 62 +++++++--------------- ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h | 30 ++++++++++- 3 files changed, 48 insertions(+), 45 deletions(-) Platforms/ARM/Juno/ArmJuno.dsc | 12 + Platforms/ARM/Juno/ArmJuno.fdf | 6 + .../ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 864 +++++++++++++++++++++ .../Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 68 ++ 4 files changed, 950 insertions(+) create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf -- 2.5.5

8 years, 5 months

Re: [Linaro-uefi] [PATCH] Platforms/ARM/Juno: Add GCC ARMv8 target architecture flag

by Alexei Fedorov

OK, You are also right that GCC:*_*_ARM_PLATFORM_FLAGS = -march=armv8-a should be used (this was my original modification, which was changed later). Alexei. -----Original Message----- From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: 27 July 2016 17:27 To: Alexei Fedorov Subject: Re: [Linaro-uefi] [PATCH] Platforms/ARM/Juno: Add GCC ARMv8 target architecture flag On 27 July 2016 at 17:58, Alexei Fedorov <Alexei.Fedorov(a)arm.com> wrote: > See below: > > "C:\Linaro_GCC\bin\arm-none-eabi-gcc" -mthumb > -Iq:\edk2/ArmPlatformPkg/ArmVExpressPkg/Include > -Iq:\edk2/ArmPlatformPkg/ArmJunoPkg/Include -g -fshort-wchar > -fno-strict-aliasing -Wall -Werror -Wno-array-bounds > -ffunction-sections -fdata-sections -c -include AutoGen.h -fno-common > -DSTRING_ARRAY_NAME=BaseMemoryLibStmStrings -g -Os -fshort-wchar > -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -c -include > AutoGen.h -fno-common -mlittle-endian -mabi=aapcs -fno-short-enums > -save-temps -funsigned-char -ffunction-sections -fdata-sections > -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft > -fstack-protector -mword-relocations -mno-unaligned-access -O0 -o > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\BaseMemoryLibStm\ > BaseMemoryLibStm\OUTPUT\.\SetMem64Wrapper.obj -Iq:\edk2\ArmPkg\Lib > rary\BaseMemoryLibStm\Arm -Iq:\edk2\ArmPkg\Library\BaseMemoryLibStm > -Iq:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\BaseMemoryLibSt > m\BaseMemoryLibStm\DEBUG -Iq:\edk2\MdePkg -Iq:\edk2\MdePkg\Include > -Iq:\edk2\MdePkg\Include\Arm -Iq:\edk2\ArmPkg -Iq:\edk2\ArmPkg\Include > q:\edk2\ArmPkg\Library\BaseMemoryLibStm\SetMem64Wrapper.c > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii: Assembler messages: > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:21: Error: attempt to use an ARM instruction on a Thumb-only processor -- `push {r4-r8}' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:23: Error: attempt to use an ARM instruction on a Thumb-only processor -- `push {r0}' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:26: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r7,[r0,#28]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:27: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r6,[r0,#24]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:28: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r5,[r0,#20]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:29: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r4,[r0,#16]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:30: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r3,[r0,#12]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:31: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r2,[r0,#8]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:32: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r1,[r0,#4]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:33: Error: attempt to use an ARM instruction on a Thumb-only processor -- `ldr r0,[r0,#0]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:35: Error: attempt to use an ARM instruction on a Thumb-only processor -- `smc #0' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:38: Error: attempt to use an ARM instruction on a Thumb-only processor -- `pop {r8}' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:42: Error: attempt to use an ARM instruction on a Thumb-only processor -- `str r3,[r8,#12]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:43: Error: attempt to use an ARM instruction on a Thumb-only processor -- `str r2,[r8,#8]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:44: Error: attempt to use an ARM instruction on a Thumb-only processor -- `str r1,[r8,#4]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:45: Error: attempt to use an ARM instruction on a Thumb-only processor -- `str r0,[r8,#0]' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:47: Error: attempt to use an ARM instruction on a Thumb-only processor -- `mov r0,r8' > Mqakefile:290: recipe for target > 'q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmc > Lib\OUTPUT\Arm\ArmSmc.obj' failed > :\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:50: Error: attempt to use an ARM instruction on a Thumb-only processor -- `pop {r4-r8}' > q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmcLib\OUTPUT\Arm\ArmSmc.iii:52: Error: attempt to use an ARM instruction on a Thumb-only processor -- `bx lr' > make: *** > [q:\edk2\Build\ArmJuno\DEBUG_GCC49\ARM\ArmPkg\Library\ArmSmcLib\ArmSmc > Lib\OUTPUT\Arm\ArmSmc.obj] Error 1 > > This error is reported by: > arm-none-eabi-gcc.exe (GNU Tools for ARM Embedded Processors) 4.9.3 > 20141119 (release) [ARM/embedded-4_9-branch revision 218278 > > but doesn't occur with: > arm-eabi-gcc.exe (Linaro GCC 4.9-2015.05) 4.9.3 20150413 (prerelease) > > , so looks like GCC internal issue. > These GCCs are simply built for different default targets. So adding -march=armv8-a to ARM's platform flags is fine by me IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

8 years, 5 months

[PATCH] Platforms/ARM/Juno: Add GCC ARMv8 target architecture flag

by evan.lloyd＠arm.com

From: Alexei <Alexei.Fedorov(a)arm.com> This commit adds the GCC compiler "-march=armv8-a" flag for the Juno platform with ARMv8 CPU. This compilation flag also fixes assembler errors like Error: attempt to use an ARM instruction on a Thumb-only processor -- `push {r4-r8}' which are reported by GCC compilers prior to Linaro GCC 4.9-2015.05 4.9.3 20150413 (i.e. 4.9.3 20141119). Code is available at: https://github.com/EvanLloyd/OpenPlatformPkg/tree/JunoBuild_v1 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov(a)arm.com> Signed-off-by: Evan Lloyd <evan.lloyd(a)arm.com> --- Platforms/ARM/Juno/ArmJuno.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc index 4f41fb159f193b3593048ce118fd0e8e97843809..87b8d517f292e81297dcf6577e5376fd7a3c8569 100644 --- a/Platforms/ARM/Juno/ArmJuno.dsc +++ b/Platforms/ARM/Juno/ArmJuno.dsc @@ -75,6 +75,7 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, Libr [BuildOptions] *_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include + *_*_*_PLATFORM_FLAGS = -march=armv8-a ################################################################################ # -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

8 years, 5 months

← Newer
1
...
36
37
38
39
40
41
42
...
82
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

Linaro-uefi