xtheadvector uses different encodings than standard vector for
vsetvli and vector loads/stores. Write the instruction formats to be
used in assembly code.
Co-developed-by: Heiko Stuebner <heiko(a)sntech.de>
Signed-off-by: Charlie Jenkins <charlie(a)rivosinc.com>
---
arch/riscv/include/asm/vendor_extensions/thead.h | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/include/asm/vendor_extensions/thead.h
index 92eec729888d..6e3c85351f82 100644
--- a/arch/riscv/include/asm/vendor_extensions/thead.h
+++ b/arch/riscv/include/asm/vendor_extensions/thead.h
@@ -16,4 +16,30 @@
extern const struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead;
+/* Extension specific helpers */
+
+/*
+ * Vector 0.7.1 as used for example on T-Head Xuantie cores, uses an older
+ * encoding for vsetvli (ta, ma vs. d1), so provide an instruction for
+ * vsetvli t4, x0, e8, m8, d1
+ */
+#define THEAD_VSETVLI_T4X0E8M8D1 ".long 0x00307ed7\n\t"
+#define THEAD_VSETVLI_X0X0E8M8D1 ".long 0x00307057\n\t"
+
+/*
+ * While in theory, the vector-0.7.1 vsb.v and vlb.v result in the same
+ * encoding as the standard vse8.v and vle8.v, compilers seem to optimize
+ * the call resulting in a different encoding and then using a value for
+ * the "mop" field that is not part of vector-0.7.1
+ * So encode specific variants for vstate_save and _restore.
+ */
+#define THEAD_VSB_V_V0T0 ".long 0x02028027\n\t"
+#define THEAD_VSB_V_V8T0 ".long 0x02028427\n\t"
+#define THEAD_VSB_V_V16T0 ".long 0x02028827\n\t"
+#define THEAD_VSB_V_V24T0 ".long 0x02028c27\n\t"
+#define THEAD_VLB_V_V0T0 ".long 0x012028007\n\t"
+#define THEAD_VLB_V_V8T0 ".long 0x012028407\n\t"
+#define THEAD_VLB_V_V16T0 ".long 0x012028807\n\t"
+#define THEAD_VLB_V_V24T0 ".long 0x012028c07\n\t"
+
#endif
--
2.44.0
This patch series ended up much larger than expected, please bear with
me! The goal here is to support vendor extensions, starting at probing
the device tree and ending with reporting to userspace.
The main design objective was to allow vendors to operate independently
of each other. This has been achieved by delegating vendor extensions to
a their own files and then accumulating the extensions in
arch/riscv/kernel/vendor_extensions.c.
Each vendor will have their own list of extensions they support.
There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 that is
used to request which thead vendor extensions are supported on the
current platform. This allows future vendors to allocate hwprobe keys
for their vendor.
On to the xtheadvector specific code. xtheadvector is a custom extension
that is based upon riscv vector version 0.7.1 [1]. All of the vector
routines have been modified to support this alternative vector version
based upon whether xtheadvector was determined to be supported at boot.
I have tested this with an Allwinner Nezha board. I ran into issues
booting the board on 6.9-rc1 so I applied these patches to 6.8. There
are a couple of minor merge conflicts that do arrise when doing that, so
please let me know if you have been able to boot this board with a 6.9
kernel. I used SkiffOS [2] to manage building the image, but upgraded
the U-Boot version to Samuel Holland's more up-to-date version [3] and
changed out the device tree used by U-Boot with the device trees that
are present in upstream linux and this series. Thank you Samuel for all
of the work you did to make this task possible.
To test the integration, I used the riscv vector kselftests. I modified
the test cases to be able to more easily extend them, and then added a
xtheadvector target that works by calling hwprobe and swapping out the
vector asm if needed.
[1] https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361…
[2] https://github.com/skiffos/SkiffOS/tree/master/configs/allwinner/nezha
[3] https://github.com/smaeul/u-boot/commit/2e89b706f5c956a70c989cd31665f1429e9…
Signed-off-by: Charlie Jenkins <charlie(a)rivosinc.com>
---
Changes in v3:
- Allow any hardware to support any vendor extension, rather than
restricting the vendor extensions to the same vendor as the hardware
- Introduce config options to enable/disable a vendor's extensions
- Link to v2: https://lore.kernel.org/r/20240415-dev-charlie-support_thead_vector_6_9-v2-…
Changes in v2:
- Added commit hash to xtheadvector
- Simplified riscv,isa vector removal fix to not mess with the DT
riscv,vendorid
- Moved riscv,vendorid parsing into a different patch and cache the
value to be used by alternative patching
- Reduce riscv,vendorid missing severity to "info"
- Separate vendor extension list to vendor files
- xtheadvector no longer puts v in the elf_hwcap
- Only patch vendor extension if all harts are associated with the same
vendor. This is the best chance the kernel has for working properly if
there are multiple vendors.
- Split hwprobe vendor keys out into vendor file
- Add attribution for Heiko's patches
- Link to v1: https://lore.kernel.org/r/20240411-dev-charlie-support_thead_vector_6_9-v1-…
---
Charlie Jenkins (15):
riscv: cpufeature: Fix thead vector hwcap removal
dt-bindings: riscv: Add xtheadvector ISA extension description
riscv: vector: Use vlenb from DT
riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
riscv: Fix extension subset checking
riscv: Extend cpufeature.c to detect vendor extensions
riscv: Introduce vendor variants of extension helpers
riscv: drivers: Convert xandespmu to use the vendor extension framework
riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
riscv: Add xtheadvector instruction definitions
riscv: vector: Support xtheadvector save/restore
riscv: hwprobe: Add thead vendor extension probing
riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
selftests: riscv: Fix vector tests
selftests: riscv: Support xtheadvector in vector tests
Conor Dooley (1):
dt-bindings: riscv: cpus: add a vlen register length property
Heiko Stuebner (1):
RISC-V: define the elements of the VCSR vector CSR
Documentation/arch/riscv/hwprobe.rst | 10 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +
.../devicetree/bindings/riscv/extensions.yaml | 10 +
arch/riscv/Kconfig | 2 +
arch/riscv/Kconfig.vendor | 32 +++
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +-
arch/riscv/errata/sifive/errata.c | 3 +
arch/riscv/errata/thead/errata.c | 3 +
arch/riscv/include/asm/cpufeature.h | 106 +++++---
arch/riscv/include/asm/csr.h | 13 +
arch/riscv/include/asm/hwcap.h | 1 -
arch/riscv/include/asm/hwprobe.h | 4 +-
arch/riscv/include/asm/sbi.h | 2 +
arch/riscv/include/asm/switch_to.h | 2 +-
arch/riscv/include/asm/vector.h | 247 +++++++++++++----
arch/riscv/include/asm/vendor_extensions.h | 82 ++++++
arch/riscv/include/asm/vendor_extensions/andes.h | 19 ++
arch/riscv/include/asm/vendor_extensions/thead.h | 45 ++++
.../include/asm/vendor_extensions/thead_hwprobe.h | 11 +
arch/riscv/include/uapi/asm/hwprobe.h | 3 +-
arch/riscv/include/uapi/asm/vendor/thead.h | 3 +
arch/riscv/kernel/Makefile | 2 +
arch/riscv/kernel/cpu.c | 40 ++-
arch/riscv/kernel/cpufeature.c | 138 +++++++---
arch/riscv/kernel/kernel_mode_vector.c | 8 +-
arch/riscv/kernel/process.c | 4 +-
arch/riscv/kernel/signal.c | 6 +-
arch/riscv/kernel/sys_hwprobe.c | 9 +
arch/riscv/kernel/vector.c | 26 +-
arch/riscv/kernel/vendor_extensions.c | 69 +++++
arch/riscv/kernel/vendor_extensions/Makefile | 5 +
arch/riscv/kernel/vendor_extensions/andes.c | 35 +++
arch/riscv/kernel/vendor_extensions/thead.c | 36 +++
.../riscv/kernel/vendor_extensions/thead_hwprobe.c | 42 +++
drivers/perf/riscv_pmu_sbi.c | 8 +-
tools/testing/selftests/riscv/vector/.gitignore | 3 +-
tools/testing/selftests/riscv/vector/Makefile | 17 +-
.../selftests/riscv/vector/v_exec_initval_nolibc.c | 93 +++++++
tools/testing/selftests/riscv/vector/v_helpers.c | 67 +++++
tools/testing/selftests/riscv/vector/v_helpers.h | 7 +
tools/testing/selftests/riscv/vector/v_initval.c | 22 ++
.../selftests/riscv/vector/v_initval_nolibc.c | 68 -----
.../selftests/riscv/vector/vstate_exec_nolibc.c | 20 +-
.../testing/selftests/riscv/vector/vstate_prctl.c | 295 ++++++++++++---------
44 files changed, 1277 insertions(+), 350 deletions(-)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240411-dev-charlie-support_thead_vector_6_9-1591fc2a431d
--
- Charlie
Hi Aaron, Jakub, all,
I have recently been exercising the Open vSwitch kernel selftests,
using vng, something like this:
TESTDIR="tools/testing/selftests/net/openvswitch"
vng -v --run . --user root --cpus 2 \
--overlay-rwdir "$PWD" -- \
"modprobe openvswitch && \
echo \"timeout=90\" >> \"${TESTDIR}/settings\" && \
make -C \"$TESTDIR\" run_tests"
And I have some observations that I'd like to ask about.
1. Building the kernel using the following command does not
build the openvswitch kernel module.
vng -v --build \
--config tools/testing/selftests/net/config
All that seems to be missing is CONFIG_OPENVSWITCH=m
and I am wondering what the best way of resolving this is.
Perhaps I am doing something wrong.
Or perhaps tools/testing/selftests/net/openvswitch/config
should be created? If so, should it include (most of?) what is in
tools/testing/selftests/net/config, or just CONFIG_OPENVSWITCH=m?
2. As per my example above, it seems that a modprobe openvswitch is
required (if openvswitch is a module).
Again, perhaps I am doing something wrong. But if not, should this be
incorporated into tools/testing/selftests/net/openvswitch/openvswitch.sh
or otherwise automated?
3. I have observed that the last test fails (yesterday, but not today!),
because the namespace it tries to create already exists. I believe this
is because it is pending deletion.
My work-around is as follows:
ovs_add_netns_and_veths () {
info "Adding netns attached: sbx:$1 dp:$2 {$3, $4, $5}"
+ for i in $(seq 10); do
+ ovs_sbx "$1" test -e "/var/run/netns/$3" || break
+ info "Namespace $3 still exists (attempt $i)"
+ ovs_sbx "$1" ip netns del "$3"
+ sleep "$i"
+ done
ovs_sbx "$1" ip netns add "$3" || return 1
on_exit "ovs_sbx $1 ip netns del $3"
ovs_sbx "$1" ip link add "$4" type veth peer name "$5" || return 1
N.B.: the "netns del" part is probably not needed,
but I'm not able to exercise it effectively right now.
I am wondering if a loop like this is appropriate to add, perhaps also
to namespace deletion. Or if it would be appropriate to port
openvswitch.sh to use ./tools/testing/selftests/net/lib.sh, which I
believe handles this.
4. I am observing timeouts whith the default value of 45s.
Bumping this to 90s seems to help.
Are there any objections to a patch to bump the timeout?
I had to explain how to run the driver tests twice already.
Improve the README so we can just point to it.
Also fix a potential problem with the SSH remote sessions.
Jakub Kicinski (4):
selftests: drv-net: force pseudo-terminal allocation in ssh
selftests: drv-net: extend the README with more info and example
selftests: drv-net: reimplement the config parser
selftests: drv-net: validate the environment
.../testing/selftests/drivers/net/README.rst | 95 ++++++++++++++++---
.../selftests/drivers/net/lib/py/env.py | 46 ++++++---
.../drivers/net/lib/py/remote_ssh.py | 2 +-
3 files changed, 118 insertions(+), 25 deletions(-)
--
2.44.0
I wanted to implement sscanf() for ksft_min_kernel_version() and this is
a prerequisite for it.
It's also useful on its own so it gets its own submission.
Signed-off-by: Thomas Weißschuh <linux(a)weissschuh.net>
---
Thomas Weißschuh (2):
tools/nolibc: add limits for {u,}intmax_t, ulong and {u,}llong
tools/nolibc: implement strtol() and friends
tools/include/nolibc/stdint.h | 19 +++++
tools/include/nolibc/stdlib.h | 109 +++++++++++++++++++++++++++
tools/testing/selftests/nolibc/nolibc-test.c | 59 +++++++++++++++
3 files changed, 187 insertions(+)
---
base-commit: f1652790cd374bcf98efc913ec69ed18d20e7747
change-id: 20240415-nolibc-strtol-af77a1f2c766
Best regards,
--
Thomas Weißschuh <linux(a)weissschuh.net>