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[PATCH 07/20] ublk: set UBLK_IO_F_INTEGRITY in ublksrv_io_desc

by Caleb Sander Mateos

Indicate to the ublk server when an incoming request has integrity data by setting UBLK_IO_F_INTEGRITY in the ublksrv_io_desc's op_flags field. Signed-off-by: Caleb Sander Mateos <csander(a)purestorage.com> --- drivers/block/ublk_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/block/ublk_drv.c b/drivers/block/ublk_drv.c index 2893a9172220..d3652ceba96d 100644 --- a/drivers/block/ublk_drv.c +++ b/drivers/block/ublk_drv.c @@ -1107,10 +1107,13 @@ static inline unsigned int ublk_req_build_flags(struct request *req) flags |= UBLK_IO_F_NOUNMAP; if (req->cmd_flags & REQ_SWAP) flags |= UBLK_IO_F_SWAP; + if (blk_integrity_rq(req)) + flags |= UBLK_IO_F_INTEGRITY; + return flags; } static blk_status_t ublk_setup_iod(struct ublk_queue *ubq, struct request *req) { -- 2.45.2

12 hours, 8 minutes

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[PATCH 04/20] ublk: add integrity UAPI

by Caleb Sander Mateos

From: Stanley Zhang <stazhang(a)purestorage.com> Add UAPI definitions for metadata/integrity support in ublk. UBLK_PARAM_TYPE_INTEGRITY and struct ublk_param_integrity allow a ublk server to specify the integrity params of a ublk device. The ublk driver will set UBLK_IO_F_INTEGRITY in the op_flags field of struct ublksrv_io_desc for requests with integrity data. The ublk server uses user copy with UBLKSRV_IO_INTEGRITY_FLAG set in the offset parameter to access a request's integrity buffer. Signed-off-by: Stanley Zhang <stazhang(a)purestorage.com> [csander: drop feature flag and redundant pi_tuple_size field, add io_desc flag, use block metadata UAPI constants] Signed-off-by: Caleb Sander Mateos <csander(a)purestorage.com> --- include/uapi/linux/ublk_cmd.h | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/ublk_cmd.h b/include/uapi/linux/ublk_cmd.h index ec77dabba45b..5bfb9a0521c3 100644 --- a/include/uapi/linux/ublk_cmd.h +++ b/include/uapi/linux/ublk_cmd.h @@ -129,11 +129,15 @@ #define UBLK_QID_BITS 12 #define UBLK_QID_BITS_MASK ((1ULL << UBLK_QID_BITS) - 1) #define UBLK_MAX_NR_QUEUES (1U << UBLK_QID_BITS) -#define UBLKSRV_IO_BUF_TOTAL_BITS (UBLK_QID_OFF + UBLK_QID_BITS) +/* Copy to/from request integrity buffer instead of data buffer */ +#define UBLK_INTEGRITY_FLAG_OFF (UBLK_QID_OFF + UBLK_QID_BITS) +#define UBLKSRV_IO_INTEGRITY_FLAG (1ULL << UBLK_INTEGRITY_FLAG_OFF) + +#define UBLKSRV_IO_BUF_TOTAL_BITS (UBLK_INTEGRITY_FLAG_OFF + 1) #define UBLKSRV_IO_BUF_TOTAL_SIZE (1ULL << UBLKSRV_IO_BUF_TOTAL_BITS) /* * ublk server can register data buffers for incoming I/O requests with a sparse * io_uring buffer table. The request buffer can then be used as the data buffer @@ -406,10 +410,12 @@ struct ublksrv_ctrl_dev_info { * * ublk server has to check this flag if UBLK_AUTO_BUF_REG_FALLBACK is * passed in. */ #define UBLK_IO_F_NEED_REG_BUF (1U << 17) +/* Request has an integrity data buffer */ +#define UBLK_IO_F_INTEGRITY (1U << 18) /* * io cmd is described by this structure, and stored in share memory, indexed * by request tag. * @@ -598,10 +604,20 @@ struct ublk_param_segment { __u32 max_segment_size; __u16 max_segments; __u8 pad[2]; }; +struct ublk_param_integrity { + __u32 flags; /* LBMD_PI_CAP_* from linux/fs.h */ + __u8 interval_exp; + __u8 metadata_size; + __u8 pi_offset; + __u8 csum_type; /* LBMD_PI_CSUM_* from linux/fs.h */ + __u8 tag_size; + __u8 pad[7]; +}; + struct ublk_params { /* * Total length of parameters, userspace has to set 'len' for both * SET_PARAMS and GET_PARAMS command, and driver may update len * if two sides use different version of 'ublk_params', same with @@ -612,16 +628,18 @@ struct ublk_params { #define UBLK_PARAM_TYPE_DISCARD (1 << 1) #define UBLK_PARAM_TYPE_DEVT (1 << 2) #define UBLK_PARAM_TYPE_ZONED (1 << 3) #define UBLK_PARAM_TYPE_DMA_ALIGN (1 << 4) #define UBLK_PARAM_TYPE_SEGMENT (1 << 5) +#define UBLK_PARAM_TYPE_INTEGRITY (1 << 6) __u32 types; /* types of parameter included */ struct ublk_param_basic basic; struct ublk_param_discard discard; struct ublk_param_devt devt; struct ublk_param_zoned zoned; struct ublk_param_dma_align dma; struct ublk_param_segment seg; + struct ublk_param_integrity integrity; }; #endif -- 2.45.2

12 hours, 8 minutes

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[PATCH 03/20] blk-integrity: take const pointer in blk_integrity_rq()

by Caleb Sander Mateos

blk_integrity_rq() doesn't modify the struct request passed in, so allow a const pointer to be passed. Use a matching signature for the !CONFIG_BLK_DEV_INTEGRITY version. Signed-off-by: Caleb Sander Mateos <csander(a)purestorage.com> --- include/linux/blk-integrity.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/blk-integrity.h b/include/linux/blk-integrity.h index a6b84206eb94..c15b1ac62765 100644 --- a/include/linux/blk-integrity.h +++ b/include/linux/blk-integrity.h @@ -89,11 +89,11 @@ static inline unsigned int bio_integrity_bytes(struct blk_integrity *bi, unsigned int sectors) { return bio_integrity_intervals(bi, sectors) * bi->metadata_size; } -static inline bool blk_integrity_rq(struct request *rq) +static inline bool blk_integrity_rq(const struct request *rq) { return rq->cmd_flags & REQ_INTEGRITY; } /* @@ -166,13 +166,13 @@ static inline unsigned int bio_integrity_intervals(struct blk_integrity *bi, static inline unsigned int bio_integrity_bytes(struct blk_integrity *bi, unsigned int sectors) { return 0; } -static inline int blk_integrity_rq(struct request *rq) +static inline bool blk_integrity_rq(const struct request *rq) { - return 0; + return false; } static inline struct bio_vec rq_integrity_vec(struct request *rq) { /* the optimizer will remove all calls to this function */ -- 2.45.2

12 hours, 8 minutes

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[PATCH 02/20] block: validate interval_exp integrity limit

by Caleb Sander Mateos

Various code assumes that the integrity interval is at least 1 sector and evenly divides the logical block size. Add these checks to blk_validate_integrity_limits(). This guards against block drivers that report invalid interval_exp values. Signed-off-by: Caleb Sander Mateos <csander(a)purestorage.com> --- block/blk-settings.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/block/blk-settings.c b/block/blk-settings.c index d138abc973bb..a9e65dc090da 100644 --- a/block/blk-settings.c +++ b/block/blk-settings.c @@ -191,12 +191,17 @@ static int blk_validate_integrity_limits(struct queue_limits *lim) return -EINVAL; } break; } - if (!bi->interval_exp) + if (!bi->interval_exp) { bi->interval_exp = ilog2(lim->logical_block_size); + } else if (bi->interval_exp < SECTOR_SHIFT || + bi->interval_exp > ilog2(lim->logical_block_size)) { + pr_warn("invalid interval_exp %u\n", bi->interval_exp); + return -EINVAL; + } /* * The PI generation / validation helpers do not expect intervals to * straddle multiple bio_vecs. Enforce alignment so that those are * never generated, and that each buffer is aligned as expected. -- 2.45.2

12 hours, 8 minutes

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[PATCH v5 4/4] selftests/resctrl: Fix non-contiguous CBM check for Hygon

by Xiaochen Shen

The resctrl selftest currently fails on Hygon CPUs that always supports non-contiguous CBM, printing the error: "# Hardware and kernel differ on non-contiguous CBM support!" This occurs because the arch_supports_noncont_cat() function lacks vendor detection for Hygon CPUs, preventing proper identification of their non-contiguous CBM capability. Fix this by adding Hygon vendor ID detection to arch_supports_noncont_cat(). Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com> --- tools/testing/selftests/resctrl/cat_test.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c index 94cfdba5308d..f00b622c1460 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -290,8 +290,10 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param static bool arch_supports_noncont_cat(const struct resctrl_test *test) { - /* AMD always supports non-contiguous CBM. */ - if (get_vendor() == ARCH_AMD) + unsigned int vendor_id = get_vendor(); + + /* AMD and Hygon always support non-contiguous CBM. */ + if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON) return true; #if defined(__i386__) || defined(__x86_64__) /* arch */ -- 2.47.3

14 hours, 38 minutes

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[PATCH v5 3/4] selftests/resctrl: Add CPU vendor detection for Hygon

by Xiaochen Shen

The resctrl selftest currently fails on Hygon CPUs that support Platform QoS features, printing the error: "# Can not get vendor info..." This occurs because vendor detection is missing for Hygon CPUs. Fix this by extending the CPU vendor detection logic to include Hygon's vendor ID. Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h index 4f9c7d04c98d..afe635b6e48d 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -39,6 +39,7 @@ */ #define ARCH_INTEL BIT(0) #define ARCH_AMD BIT(1) +#define ARCH_HYGON BIT(2) #define END_OF_TESTS 1 diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c index 42605e2a3b66..dbcd5eea9fbc 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -50,6 +50,8 @@ static unsigned int detect_vendor(void) vendor_id = ARCH_INTEL; else if (s && !strcmp(s, ": AuthenticAMD\n")) vendor_id = ARCH_AMD; + else if (s && !strcmp(s, ": HygonGenuine\n")) + vendor_id = ARCH_HYGON; fclose(inf); free(res); -- 2.47.3

14 hours, 38 minutes

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[PATCH v5 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes

by Xiaochen Shen

The resctrl selftest currently exhibits several failures on Hygon CPUs due to missing vendor detection and edge-case handling specific to Hygon's architecture. This patch series addresses three distinct issues: 1. A division-by-zero crash in SNC detection on some platforms (e.g., Hygon). 2. Missing CPU vendor detection, causing the test to fail with "# Can not get vendor info..." on Hygon CPUs. 3. Incorrect handling of non-contiguous CBM support on Hygon CPUs. These changes enable resctrl selftest to run successfully on Hygon CPUs that support Platform QoS features. Maintainer notes: ----------------- Patch 1: selftests/resctrl: Fix a division by zero error on Hygon - This is a candidate for backport with "Fixes:" tag. Patch 2: selftests/resctrl: Define CPU vendor IDs as bits to match usage - This is *not* a candidate for backport since it is an enhancement and preparatory patch for patch 3. Patch 3: selftests/resctrl: Add CPU vendor detection for Hygon Patch 4: selftests/resctrl: Fix non-contiguous CBM check for Hygon - Even though they are fixes they are *not* candidates for backport since they are based on another patch series (x86/resctrl: Fix Platform QoS issues for Hygon) which is in process of being added to resctrl. ----------------- Changelog: v5: - Patch 2: 1. Fix a nit of "reverse fir ordering" of the variable declarations in detect_vendor() in v4 patch series (Reinette). 2. Add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com>. v4: - Cover letter: add maintainer notes outlining how these patches to be handled (Reinette). - Re-organize the patch series to move original patch 3 to the beginning of series. The patch order has changed between v3 and v4 (Reinette): v3 -> v4 patch #3 -> patch #1 patch #1 -> patch #2 patch #2 -> patch #3 patch #4 -> patch #4 - Patch 2: 1. Resolve a conflict against latest upstream kernel (Reinette). 2. Fix a nit to maintain the reverse fir ordering of variables in detect_vendor() (Reinette). - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 4: move the maintainer note into the cover letter (Reinette). v3: - Patch 1: 1. Update the return types of detect_vendor() and get_vendor() from 'int' to 'unsigned int' to align with their usage as bitmask values and to prevent potentially risky type conversions (Fenghua). 2. Split the code changes of "define CPU vendor IDs as bits to match usage" from original patch 1 into a separate patch (this patch, suggested by Fenghua and Reinette). 3. Introduce the flag 'initialized' to simplify the get_vendor() -> detect_vendor() logic (Reinette). - Patch 2 (original patch 1): 1. Move the code changes of "define CPU vendor IDs as bits to match usage" into patch 1. - Patch 3 (original patch 2): 1. Fix a nit of code comment for affected platforms (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. - Patch 4 (original patch 3): 1. Fix a nit to avoid calling get_vendor() twice (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. v2: - Patch 1: switch all of the vendor id bitmasks to use BIT() (Reinette) - Patch 2: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> add a maintainer note to highlight it is not a candidate for backport (Reinette) Xiaochen Shen (4): selftests/resctrl: Fix a division by zero error on Hygon selftests/resctrl: Define CPU vendor IDs as bits to match usage selftests/resctrl: Add CPU vendor detection for Hygon selftests/resctrl: Fix non-contiguous CBM check for Hygon tools/testing/selftests/resctrl/cat_test.c | 6 ++-- tools/testing/selftests/resctrl/resctrl.h | 8 ++++-- .../testing/selftests/resctrl/resctrl_tests.c | 28 +++++++++++++------ tools/testing/selftests/resctrl/resctrlfs.c | 10 +++++++ 4 files changed, 39 insertions(+), 13 deletions(-) -- 2.47.3

14 hours, 38 minutes

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[PATCH v5 1/4] selftests/resctrl: Fix a division by zero error on Hygon

by Xiaochen Shen

Commit a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled") introduced the snc_nodes_per_l3_cache() function to detect the Intel Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs sharing LLC with CPU0. The function was designed to return: (1) >1: SNC mode is enabled. (2) 1: SNC mode is not enabled or not supported. However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually less than #CPUs in node0. This results in snc_nodes_per_l3_cache() returning 0 (calculated as cache_cpus / node_cpus). This leads to a division by zero error in get_cache_size(): *cache_size /= snc_nodes_per_l3_cache(); Causing the resctrl selftest to fail with: "Floating point exception (core dumped)" Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC mode is not supported on the platform. Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled") Signed-off-by: Xiaochen Shen <shenxiaochen(a)open-hieco.net> Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com> --- tools/testing/selftests/resctrl/resctrlfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/selftests/resctrl/resctrlfs.c index 195f04c4d158..b9c1bfb6cc02 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -243,6 +243,16 @@ int snc_nodes_per_l3_cache(void) } snc_mode = cache_cpus / node_cpus; + /* + * On some platforms (e.g. Hygon), + * cache_cpus < node_cpus, the calculated snc_mode is 0. + * + * Set snc_mode = 1 to indicate that SNC mode is not + * supported on the platform. + */ + if (!snc_mode) + snc_mode = 1; + if (snc_mode > 1) ksft_print_msg("SNC-%d mode discovered.\n", snc_mode); } -- 2.47.3

14 hours, 38 minutes

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[PATCH v4 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes

by Xiaochen Shen

The resctrl selftest currently exhibits several failures on Hygon CPUs due to missing vendor detection and edge-case handling specific to Hygon's architecture. This patch series addresses three distinct issues: 1. A division-by-zero crash in SNC detection on some platforms (e.g., Hygon). 2. Missing CPU vendor detection, causing the test to fail with "# Can not get vendor info..." on Hygon CPUs. 3. Incorrect handling of non-contiguous CBM support on Hygon CPUs. These changes enable resctrl selftest to run successfully on Hygon CPUs that support Platform QoS features. Maintainer notes: ----------------- Patch 1: selftests/resctrl: Fix a division by zero error on Hygon - This is a candidate for backport with "Fixes:" tag. Patch 2: selftests/resctrl: Define CPU vendor IDs as bits to match usage - This is *not* a candidate for backport since it is an enhancement and preparatory patch for patch 3. Patch 3: selftests/resctrl: Add CPU vendor detection for Hygon Patch 4: selftests/resctrl: Fix non-contiguous CBM check for Hygon - Even though they are fixes they are *not* candidates for backport since they are based on another patch series (x86/resctrl: Fix Platform QoS issues for Hygon) which is in process of being added to resctrl. ----------------- Changelog: v4: - Cover letter: add maintainer notes outlining how these patches to be handled (Reinette). - Re-organize the patch series to move original patch 3 to the beginning of series. The patch order has changed between v3 and v4 (Reinette): v3 -> v4 patch #3 -> patch #1 patch #1 -> patch #2 patch #2 -> patch #3 patch #4 -> patch #4 - Patch 2: 1. Resolve a conflict against latest upstream kernel (Reinette). 2. Fix a nit to maintain the reverse fir ordering of variables in detect_vendor() (Reinette). - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 4: move the maintainer note into the cover letter (Reinette). v3: - Patch 1: 1. Update the return types of detect_vendor() and get_vendor() from 'int' to 'unsigned int' to align with their usage as bitmask values and to prevent potentially risky type conversions (Fenghua). 2. Split the code changes of "define CPU vendor IDs as bits to match usage" from original patch 1 into a separate patch (this patch, suggested by Fenghua and Reinette). 3. Introduce the flag 'initialized' to simplify the get_vendor() -> detect_vendor() logic (Reinette). - Patch 2 (original patch 1): 1. Move the code changes of "define CPU vendor IDs as bits to match usage" into patch 1. - Patch 3 (original patch 2): 1. Fix a nit of code comment for affected platforms (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. - Patch 4 (original patch 3): 1. Fix a nit to avoid calling get_vendor() twice (Fenghua). 2. Add Reviewed-by: Fenghua Yu <fenghuay(a)nvidia.com>. v2: - Patch 1: switch all of the vendor id bitmasks to use BIT() (Reinette) - Patch 2: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre(a)intel.com> add a maintainer note to highlight it is not a candidate for backport (Reinette) Xiaochen Shen (4): selftests/resctrl: Fix a division by zero error on Hygon selftests/resctrl: Define CPU vendor IDs as bits to match usage selftests/resctrl: Add CPU vendor detection for Hygon selftests/resctrl: Fix non-contiguous CBM check for Hygon tools/testing/selftests/resctrl/cat_test.c | 6 ++-- tools/testing/selftests/resctrl/resctrl.h | 8 ++++-- .../testing/selftests/resctrl/resctrl_tests.c | 28 +++++++++++++------ tools/testing/selftests/resctrl/resctrlfs.c | 10 +++++++ 4 files changed, 39 insertions(+), 13 deletions(-) -- 2.47.3

15 hours, 6 minutes

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[PATCH v5 00/24] ARM64 PMU Partitioning

by Colton Lewis

This series creates a new PMU scheme on ARM, a partitioned PMU that allows reserving a subset of counters for more direct guest access, significantly reducing overhead. More details, including performance benchmarks, can be read in the v1 cover letter linked below. An overview of what this series accomplishes was presented at KVM Forum 2025. Slides [1] and video [2] are linked below. The long duration between v4 and v5 is due to time spent on this project being monopolized preparing this feature for internal production. As a result, there are too many improvements to fully list here, but I will cover the notable ones. v5: * Rebase onto v6.18-rc7. This required pulling some reorganization patches from Anish and Sean that were dependencies from previous versions based on kvm/queue but never made it to upstream. * Ensure FGTs (fine-grained traps) are correctly programmed at vCPU load using kvm_vcpu_load_fgt() and helpers introduced by Oliver Upton. * Cleanly separate concerns of whether the partitioned PMU is enabled for the guest and whether FGT should be enabled. This allows that the capability can be VM-scoped while the implementation detail of whether FGT and context switching are in effect can remain vCPU-scoped. * Shrink the uAPI change. Instead of a cap and corresponding ioctl, the feature can be controlled by just a cap with an argument. The cap is now also VM-scoped and enforces ordering that it should be decided before vCPUs are created. Whether the cap is enabled is now tracked by the new flag KVM_ARCH_ARM_PARTITIONED_PMU_ENABLED. * Improve log messages when partitioning in the PMUv3 driver. * Introduce a global variable armv8pmu_hpmn_max in the PMUv3 driver so KVM code can read if a value was set before the PMU is probed. This is needed to properly test if we have the capability before vCPUs are created. * Make it possible for a VMM to filter the HPMN0 feature bit. * Fix event filter problems with PMEVTYPER handling in writethrough_pmevtyper() and kvm_pmu_apply_event_filter() by using kvm_pmu_event_mask() in the right spots. And if an event is filtered, write the physical register with the appropriate exclude bits set but keep the virtual register exactly what the guest wrote. * Fix register access problems with the PMU register fast path handler by lifting some static PMU access checks from sys_regs.c to use them in the fast path too and make bit masking more strict for better ARM compliance. * Fix the readability and logic of programming the MDCR_EL2 register when entering the guest. Make sure to set the HPME bit to allow host counters to count guest events. Set TPM and TPMCR by default and clear them if partitioning is enabled rather than the previous inverted logic of leaving them clear and setting them if partitioning is not enabled. Make the HPMN field computation more clear. * As part of lazy context switching, do a load when the guest is switching to physical access to ensure any previous writes that only reached the virtual registers reach the physical ones as well and are not clobbered by the next vcpu_put(). * Other fixes and improvements that are too small to mention or left out from my personal notes. v4: https://lore.kernel.org/kvmarm/20250714225917.1396543-1-coltonlewis@google.… v3: https://lore.kernel.org/kvm/20250626200459.1153955-1-coltonlewis@google.com/ v2: https://lore.kernel.org/kvm/20250620221326.1261128-1-coltonlewis@google.com/ v1: https://lore.kernel.org/kvm/20250602192702.2125115-1-coltonlewis@google.com/ [1] https://gitlab.com/qemu-project/kvm-forum/-/raw/main/_attachments/2025/Opti… [2] https://www.youtube.com/watch?v=YRzZ8jMIA6M&list=PLW3ep1uCIRfxwmllXTOA2txfD… Anish Ghulati (1): KVM: arm64: Move arm_{psci,hypercalls}.h to an internal KVM path Colton Lewis (20): arm64: cpufeature: Add cpucap for HPMN0 KVM: arm64: Reorganize PMU functions perf: arm_pmuv3: Introduce method to partition the PMU perf: arm_pmuv3: Generalize counter bitmasks perf: arm_pmuv3: Keep out of guest counter partition KVM: arm64: Set up FGT for Partitioned PMU KVM: arm64: Writethrough trapped PMEVTYPER register KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned KVM: arm64: Writethrough trapped PMOVS register KVM: arm64: Write fast path PMU register handlers KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU KVM: arm64: Account for partitioning in PMCR_EL0 access KVM: arm64: Context swap Partitioned PMU guest registers KVM: arm64: Enforce PMU event filter at vcpu_load() KVM: arm64: Implement lazy PMU context swaps perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters KVM: arm64: Inject recorded guest interrupts KVM: arm64: Add KVM_CAP to partition the PMU KVM: selftests: Add find_bit to KVM library KVM: arm64: selftests: Add test case for partitioned PMU Marc Zyngier (1): KVM: arm64: Reorganize PMU includes Sean Christopherson (2): KVM: arm64: Include KVM headers to get forward declarations KVM: arm64: Move ARM specific headers in include/kvm to arch directory Documentation/virt/kvm/api.rst | 24 + arch/arm/include/asm/arm_pmuv3.h | 28 + arch/arm64/include/asm/arm_pmuv3.h | 61 +- .../arm64/include/asm/kvm_arch_timer.h | 2 + arch/arm64/include/asm/kvm_host.h | 24 +- .../arm64/include/asm/kvm_pmu.h | 142 ++++ arch/arm64/include/asm/kvm_types.h | 7 +- .../arm64/include/asm/kvm_vgic.h | 0 arch/arm64/kernel/cpufeature.c | 8 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arch_timer.c | 5 +- arch/arm64/kvm/arm.c | 23 +- {include => arch/arm64}/kvm/arm_hypercalls.h | 0 {include => arch/arm64}/kvm/arm_psci.h | 0 arch/arm64/kvm/config.c | 34 +- arch/arm64/kvm/debug.c | 31 +- arch/arm64/kvm/guest.c | 2 +- arch/arm64/kvm/handle_exit.c | 2 +- arch/arm64/kvm/hyp/Makefile | 6 +- arch/arm64/kvm/hyp/include/hyp/switch.h | 211 ++++- arch/arm64/kvm/hyp/nvhe/switch.c | 4 +- arch/arm64/kvm/hyp/vhe/switch.c | 4 +- arch/arm64/kvm/hypercalls.c | 4 +- arch/arm64/kvm/pmu-direct.c | 464 +++++++++++ arch/arm64/kvm/pmu-emul.c | 678 +--------------- arch/arm64/kvm/pmu.c | 726 ++++++++++++++++++ arch/arm64/kvm/psci.c | 4 +- arch/arm64/kvm/pvtime.c | 2 +- arch/arm64/kvm/reset.c | 3 +- arch/arm64/kvm/sys_regs.c | 110 +-- arch/arm64/kvm/trace_arm.h | 2 +- arch/arm64/kvm/trng.c | 2 +- arch/arm64/kvm/vgic/vgic-debug.c | 2 +- arch/arm64/kvm/vgic/vgic-init.c | 2 +- arch/arm64/kvm/vgic/vgic-irqfd.c | 2 +- arch/arm64/kvm/vgic/vgic-kvm-device.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio-v2.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio.c | 4 +- arch/arm64/kvm/vgic/vgic-v2.c | 2 +- arch/arm64/kvm/vgic/vgic-v3-nested.c | 3 +- arch/arm64/kvm/vgic/vgic-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-v5.c | 2 +- arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 6 +- drivers/perf/arm_pmuv3.c | 137 +++- include/linux/perf/arm_pmu.h | 1 + include/linux/perf/arm_pmuv3.h | 14 +- include/uapi/linux/kvm.h | 1 + tools/include/uapi/linux/kvm.h | 1 + tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/arm64/vpmu_counter_access.c | 77 +- tools/testing/selftests/kvm/lib/find_bit.c | 1 + 53 files changed, 2049 insertions(+), 831 deletions(-) rename include/kvm/arm_arch_timer.h => arch/arm64/include/asm/kvm_arch_timer.h (98%) rename include/kvm/arm_pmu.h => arch/arm64/include/asm/kvm_pmu.h (61%) rename include/kvm/arm_vgic.h => arch/arm64/include/asm/kvm_vgic.h (100%) rename {include => arch/arm64}/kvm/arm_hypercalls.h (100%) rename {include => arch/arm64}/kvm/arm_psci.h (100%) create mode 100644 arch/arm64/kvm/pmu-direct.c create mode 100644 tools/testing/selftests/kvm/lib/find_bit.c base-commit: ac3fd01e4c1efce8f2c054cdeb2ddd2fc0fb150d -- 2.52.0.239.gd5f0c6e74e-goog

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