Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string

On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote:

The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.

Let us detect Zicond extension from ISA string available through DT or ACPI.

Signed-off-by: Anup Patel apatel@ventanamicro.com

Same applies here w.r.t. splitting in two.

Thanks, Conor.

---

Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cad8ef68eca7..7ea90e2dbc5b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification.

•    - const: zicond
  

•      description:
  

•        The standard Zicond extension for conditional arithmetic and
  

•        conditional-select/move operations as ratified in commit 8fb6694
  

•        ("Update Gemfile") of riscv-zicond.
  

•    - const: zicsr
       description: |
         The standard Zicsr extension for control and status register
  

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7efe9e2fa89..15bafc02ffd4 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -60,6 +60,7 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45 #define RISCV_ISA_EXT_MAX 64 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3a31d34fe709..49b6551f3347 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),

• __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),

-- 2.34.1