On Thu, Jul 09, 2020 at 09:27:43AM -0700, Andy Lutomirski wrote:
On Thu, Jul 9, 2020 at 9:22 AM Dave Hansen dave.hansen@intel.com wrote:
On 7/9/20 9:07 AM, Andy Lutomirski wrote:
On Thu, Jul 9, 2020 at 8:56 AM Dave Hansen dave.hansen@intel.com wrote:
On 7/9/20 8:44 AM, Andersen, John wrote:
Bits which are allowed to be pinned default to WP for CR0 and SMEP, SMAP, and UMIP for CR4.I think it also makes sense to have FSGSBASE in this set.
I know it hasn't been tested, but I think we should do the legwork to test it. If not in this set, can we agree that it's a logical next step?
I have no objection to pinning FSGSBASE, but is there a clear description of the threat model that this whole series is meant to address? The idea is to provide a degree of protection against an attacker who is able to convince a guest kernel to write something inappropriate to CR4, right? How realistic is this?
If a quick search can find this:
https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-p...
I'd pretty confident that the guys doing actual bad things have it in their toolbox too.
True, but we have the existing software CR4 pinning. I suppose the virtualization version is stronger.
Yes, as Kees said this will be stronger because it stops ROP and other gadget based techniques which avoid the use of native_write_cr0/4().
With regards to what should be done in this patchset and what in other patchsets. I have a fix for kexec thanks to Arvind's note about TRAMPOLINE_32BIT_CODE_SIZE. The physical host boots fine now and the virtual one can kexec fine.
What remains to be done on that front is to add some identifying information to the kernel image to declare that it supports paravirtualized control register pinning or not.
Liran suggested adding a section to the built image acting as a flag to signify support for being kexec'd by a kernel with pinning enabled. If anyone has any opinions on how they'd like to see this implemented please let me know. Otherwise I'll just take a stab at it and you'll all see it hopefully in the next version.
With regards to FSGSBASE, are we open to validating and adding that to the DEFAULT set as a part of a separate patchset? This patchset is focused on replicating the functionality we already have natively.
(If anyone got this email twice, sorry I messed up the From: field the first time around)
On Tue, Jul 14, 2020 at 05:39:30AM +0000, Andersen, John wrote:
With regards to FSGSBASE, are we open to validating and adding that to the DEFAULT set as a part of a separate patchset? This patchset is focused on replicating the functionality we already have natively.
Kees added FSGSBASE pinning in commit a13b9d0b97211 ("x86/cpu: Use pinning mask for CR4 bits needing to be 0"), so I believe it's a done deal already.
On Tue, Jul 14, 2020 at 09:41:29PM -0700, Sean Christopherson wrote:
On Tue, Jul 14, 2020 at 05:39:30AM +0000, Andersen, John wrote:
With regards to FSGSBASE, are we open to validating and adding that to the DEFAULT set as a part of a separate patchset? This patchset is focused on replicating the functionality we already have natively.
Kees added FSGSBASE pinning in commit a13b9d0b97211 ("x86/cpu: Use pinning mask for CR4 bits needing to be 0"), so I believe it's a done deal already.
Ah my bad. Thanks, I'll look into it.
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Andersen, John -
Sean Christopherson