CoreSight November 2017

coresight@lists.linaro.org

7 participants
7 discussions

by marekzmyslowski

Hello Mathieu, Thank for the config file. It works. I was able to build the OpenCSD kernel (form the perf-opencsd-master branch) and install on the USB (I used the ArchLinuxARM-aarch64-latest.tar.gz). I also built the perf tool (make -C tools/perf). Everything is booting but the perf has some issues: [root@alarm home]# ./perf record -vvv -e cs_etm/(a)20070000.etr/u --per-thread uname map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir Problems setting modules path maps, continuing anyway... ------------------------------------------------------------ perf_event_attr: type 8 size 112 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 enable_on_exec 1 sample_id_all 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 4 ------------------------------------------------------------ perf_event_attr: type 1 size 112 config 0x9 { sample_period, sample_freq } 1 sample_type IP|TID|IDENTIFIER read_format ID disabled 1 exclude_kernel 1 exclude_hv 1 mmap 1 comm 1 enable_on_exec 1 task 1 sample_id_all 1 mmap2 1 comm_exec 1 ------------------------------------------------------------ sys_perf_event_open: pid 2242 cpu -1 group_fd -1 flags 0x8 = 5 mmap size 528384B AUX area mmap length 4194304 perf event ring buffer mmapped per thread failed to mmap AUX area failed to mmap with 12 (Cannot allocate memory) I fixed the "map_groups__set_modules_path_dir: cannot open /lib/modules/4.13.0-rc1-ge565ad6 dir" issue by adding appropriate symbolic link but I still have an issue with the mmap. Any idea what can be wrong here (below limits that I have on my Juno)? [root@alarm ~]# ulimit -a core file size (blocks, -c) unlimited data seg size (kbytes, -d) unlimited scheduling priority (-e) 0 file size (blocks, -f) unlimited pending signals (-i) 31798 max locked memory (kbytes, -l) 64 max memory size (kbytes, -m) unlimited open files (-n) 1024 pipe size (512 bytes, -p) 8 POSIX message queues (bytes, -q) 819200 real-time priority (-r) 0 stack size (kbytes, -s) 8192 cpu time (seconds, -t) unlimited max user processes (-u) 31798 virtual memory (kbytes, -v) unlimited file locks (-x) unlimited [root@alarm ~]# Regards Marek W dniu 2017-08-18 16:54:42 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > On 18 August 2017 at 04:22, marekzmyslowski > <marekzmyslowski(a)poczta.onet.pl> wrote: > > Hello Mathieu, > > > > I've decided that currently I don't need Android. The Linux is enough. > > That is probably a better place to start. > > > However I have another issue. I've downloaded the perf-opencsd-master branch. I run the config with the ARCH=arm64 and CROSS_COMPLIE=aarch64-linux-gnu- and added support for Versatile board. Then I compiled kernel - everything was OK. Next I built the USB using the following instruction: > > https://archlinuxarm.org/platforms/armv8/arm/juno (it works fine. The linux boot on the Juno). > > Next I copied the Image file and juno.dtb into the USB but it doesn't boot. It hangs here: > > > > initrd: address 0x0 > > initrd: length 0x0 > > PEI 1132 ms > > DXE 1695 ms > > BDS 368934875444 ms > > BDS 368934873448 ms > > BDS 1535 ms > > Total Time = 368934871781 ms > > > > linux: address 0x80080000 > > linux: length 0x1150200 > > fdt: address 0x9FE00000 > > fdt: length 0x5F54 > > > > Any idea what I'm doing wrong? Any help will be appreciated (I'm so close to have Juno + CoreSight + perf :) ) > > I can't help you with booting the board itself. The best I can do is > advise to use u-boot instead of UEFI and give you my kernel .config > file (attached). For the rest there is plenty of documentation out > there. > > > > > Regards > > Marek > > > > W dniu 2017-08-16 23:08:04 użytkownik Mathieu Poirier <mathieu.poirier(a)linaro.org> napisał: > >> Hello Marek, > >> > >> Please CC the CoreSight mailing list when asking questions as someone > >> else may also be able to answer. > >> > >> First and foremost I advise using the official CoreSight kernel found > >> on the openCSD site [1] rather than my personal branch [2] - you > >> never know what you'll get with the latter. > >> > >> That being said the CoreSight kernel on the openCSD site is not an > >> Android kernel - it is simply a mainline kernel supplemented with > >> patches that haven't made their way to mainline yet. You will have to > >> either add the android patches to the CoreSight kernel or the other > >> way around (CoreSight patches on android kernel). > >> > >> Android user space is also different and does not include the > >> perf-tools. You will have to add them manually along with the > >> dependencies they require. I haven't gone through that process and as > >> such can't advise more on that portion. > >> > >> Get back to me with your questions if the above isn't sufficient. > >> > >> Best regards, > >> Mathieu > >> > >> [1]. https://github.com/Linaro/OpenCSD/tree/perf-opencsd-master > >> [2]. https://git.linaro.org/people/mathieu.poirier/coresight.git/ > >> > >> On 16 August 2017 at 14:32, marekzmyslowski > >> <marekzmyslowski(a)poczta.onet.pl> wrote: > >> > Hello Mathieu, > >> > > >> > I'm sorry for bothering but I think you may be person that can help me. I'm trying to install and run Android on Juno Board r0. I tested Android 17.05 from Linaro and it works. Now I'm trying to have a perf using Coresight but I'm little confused. Do I need to build Android from Linaro and the kernel from here https://git.linaro.org/people/mathieu.poirier/coresight.git/ or here https://github.com/Linaro/OpenCSD/tree/perf-opencsd-4.12. > >> > Any help with this will be appreciated :) > >> > > >> > Regards > >> > Marek Zmysłowski > >> > > > > > > >

6 years, 7 months

[PATCH v2 00/23] Add support for CoreSight trace decoding

by Tor Jeremiassen

Hi, This patchset adds support for user space decoding of CoreSight traces [1] of the ARM architecture. Kernel support for configuring CoreSight tracers and collect the hardware trace data in the auxtrace section of the perf.data file is already integrated [2]. The user space implementation mirrors to a large degree that of the Intel Processor Trace (PT) [3] implementation, except that the decoder library itself is separate from the perf tool sources, and is built and maintained as a separate open source project [4]. Instead, this patch set includes the necessary code and build settings to interfaces to the decoder library. This approach was chosen as the decoder library has uses outside the perf toolset and on non-linux platforms. The decoder library interface code in this patch set only supports ETMv4 trace decoding, though the library itself supports a broader range. Future patches will add support for more versions of the ARM ETM trace encoding. The trace decoder library used with this patch set is the most recent version with tag v0.7.3 This patch set, instead of being based on commits in my private branch, has been applied to a new copy of the perf-opencsd-master branch of [4] and pushed to [5] with the same perf-opencsd-master branch name. Changes since last revision: Given this is the second time it is sent out to the new audience on coresight(a)lists.linaro.org, I am resetting the version number to 2 to avoid confusion with previous mailings with a more restricted audience. Two additional commits have been added to the patches in this patch set to be fully compatible with the most recent version of the decoder library. The previous patch set assumed an older version. [1] https://lwn.net/Articles/626463 [2] https://github.com/torvalds/linux/tree/master/drivers/hwtracing/coresight [3] https://lwn.net/Articles/648154 [4] https://github.com/Linaro/OpenCSD [5] https://github.com/tor-jeremiassen/OpenCSD Tor Jeremiassen (23): perf tools: Add initial hooks for decoding coresight traces perf tools: Add processing of coresight metadata perf tools: Add coresight trace decoder library interface perf tools: Add data block processing function perf tools: Add channel context item to track packet sources perf tools: Add etmv4i packet printing capability perf tools: Add decoder new and free perf tools: Add trace packet print for dump_trace option perf tools: Add code to process the auxtrace perf event perf tools: Add function to read data from dsos perf tools: Add mapping from cpu to cs_etm_queue perf tools: Add functions to allocate and free queues perf tools: Add functions to setup and initialize queues perf tools: Add functions to allocate and free queues perf tools: Add function to get trace data from aux buffer perf tools: Add function to run the trace decoder and process samples perf tools: Add functions to process queues and run the trace decoder perf tools: Add perf event processing perf tools: Add processing of queues when events are flushed perf tools: Add synth_events and supporting functions perf tools: Add function to clear the decoder packet buffer perf tools: Add functions for full etmv4i packet decode MAINTAINERS: Adding entry for CoreSight trace decoding MAINTAINERS | 3 +- tools/perf/Makefile.config | 26 + tools/perf/util/Build | 6 + tools/perf/util/auxtrace.c | 2 + tools/perf/util/cs-etm-decoder/Build | 2 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 581 +++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 138 +++ tools/perf/util/cs-etm.c | 1180 +++++++++++++++++++++++ tools/perf/util/cs-etm.h | 50 + 9 files changed, 1987 insertions(+), 1 deletion(-) create mode 100644 tools/perf/util/cs-etm-decoder/Build create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-decoder.h create mode 100644 tools/perf/util/cs-etm.c -- 2.7.4

7 years

[PATCH] coresight: Fix disabling of CoreSight TPIU

by Robert Walker

The CoreSight TPIU should be disabled when tracing to other sinks to allow them to operate at full bandwidth. This patch fixes tpiu_disable_hw() to correctly disable the TPIU by configuring the TPIU to stop on flush, initiating a manual flush, waiting for the flush to complete and then waits for the TPIU to indicate it has stopped. Signed-off-by: Robert Walker <robert.walker(a)arm.com> --- drivers/hwtracing/coresight/coresight-tpiu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index bef49a3..4b46c49 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -46,8 +46,11 @@ #define TPIU_ITATBCTR0 0xef8 /** register definition **/ +/* FFSR - 0x300 */ +#define FFSR_FT_STOPPED BIT(1) /* FFCR - 0x304 */ #define FFCR_FON_MAN BIT(6) +#define FFCR_STOP_FI BIT(12) /** * @base: memory mapped base address for this component. @@ -85,10 +88,14 @@ static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - /* Clear formatter controle reg. */ - writel_relaxed(0x0, drvdata->base + TPIU_FFCR); + /* Clear formatter and stop on flush */ + writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); /* Generate manual flush */ - writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR); + writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); + /* Wait for flush to complete */ + coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN, 0); + /* Wait for formatter to stop */ + coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED, 1); CS_LOCK(drvdata->base); } -- 1.9.1

7 years

[PATCH v2 0/4] coresight: support panic dump functionality

by Leo Yan

### Introduction ### Embedded Trace Buffer (ETB) provides on-chip storage of trace data, usually has buffer size from 2KB to 8KB. These data has been used for profiling and this has been well implemented in coresight driver. This patch set is to explore ETB RAM data for postmortem debugging. We could consider ETB RAM data is quite useful for postmortem debugging, especially if the hardware design with local ETB buffer (ARM DDI 0461B) chapter 1.2.7. 'Local ETF', with this kind design every CPU has one dedicated ETB RAM. So it's quite handy that we can use alive CPU to help dump the hang CPU ETB RAM. Then we can quickly get to know what's the exact execution flow before its hang. Due ETB RAM buffer has small size, if all CPUs shared one ETB buffer then the trace data for causing error is easily to be overwritten by other PEs; but even so sometimes we still have chance to go through the trace data to assist debugging panic issues. ### Implementation ### Firstly we need provide a unified APIs for panic dump functionality, so it can be easily extended to enable panic dump for multiple drivers. This is finished by patch 0001, it registers panic notifier, and provide the general APIs {coresight_dump_add|coresight_dump_del} as helper functions so any coresight device can add into dump list or delete itself as needed. Generally coresight devices can add itself into panic dump when registration, if the coresight device wants to do dump it will set its 'panic_cb' in the ops structure. So patch 0002 is to add and delete panic dump node for devices. Patch 0003 and 0004 are to add panic callback functions for tmc and etm4x drivers; so tmc dirver can save specific trace data for ETB/ETF when panic happens, and etm4x driver can save metadata for offline analysis. ### Usage ### Below are the example for how to use panic dump functionality on 96boards Hikey, the brief flow is: when the panic happens the ETB panic callback function saves trace data into memory, then relies on kdump to use recovery kernel to save DDR content as kernel core dump file; after we transfer kernel core dump file from board to host PC, use 'crash' tool + extension program to extract trace data and generate 'perf' format compatible file. - Enable tracing on Hikey; in theory there have two methods to enable tracing: The first method is to use sysfs interface to enable coresight tracing: echo 1 > /sys/bus/coresight/devices/f6402000.etf/enable_sink echo 1 > /sys/bus/coresight/devices/f659c000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f659d000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f659e000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f659f000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f65dc000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f65dd000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f65de000.etm/enable_source echo 1 > /sys/bus/coresight/devices/f65df000.etm/enable_source The second method is to use tool 'perf' with snapshot method, this command is expected to enable tracing and wait for specific event happen and capture the snapshot trace data, this method also can be smoothly used for panic dump. This command currently is failure on Hikey due now coresight only support '--per-thread' method with perf tool: ./perf record --snapshot -S8196 -e cs_etm/(a)f6402000.etf/ -- sleep 1000 & - Load recovery kernel for kdump: ARM64's kdump supports to use the same kernel image both for main kernel and dump-capture kernel; so we can simply to load dump-capture kernel with below command: ./kexec -p vmlinux --dtb=hi6220-hikey.dtb --append="root=/dev/mmcblk0p9 rw maxcpus=1 reset_devices earlycon=pl011,0xf7113000 nohlt initcall_debug console=tty0 console=ttyAMA3,115200 clk_ignore_unused" - Download kernel dump file: After kernel panic happens, the kdump launches dump-capture kernel; so we need save kernel's dump file on target: cp /proc/vmcore ./vmcore Finally we can copy 'vmcore' file onto PC. - Use 'crash' tool + csdump.so extension to extract trace data: After we download vmcore file from Hikey board to host PC, we can use 'crash' tool + csdump.so to generate 'perf.data' file: ./crash vmcore vmlinux crash> extend csdump.so crash> csdump output_dir We can see in the 'output_dir' there will generate out three files: output_dir/ ├── cstrace.bin -> trace raw data ├── metadata.bin -> meta data └── perf.data -> 'perf' format compatible file The source code of 'csdump.so' will be sent to mailing list sepeartely. - User 'perf' tool for offline analysis: On Hikey board: ./perf script -v -F cpu,event,ip -i perf_2.data -k vmlinux [001] instructions: ffff000008559ad0 [001] instructions: ffff000008559230 [001] instructions: ffff00000855924c [001] instructions: ffff000008559ae0 [001] instructions: ffff000008559ad0 [001] instructions: ffff000008559230 [001] instructions: ffff00000855924c [001] instructions: ffff000008559ae0 [001] instructions: ffff000008559ad0 Changes from v1: * Add support to dump ETMv4 meta data. * Wrote 'crash' extension csdump.so so rely on it to generate 'perf' format compatible file. * Refactored panic dump driver to support pre & post panic dump. Changes from RFC: * Follow Mathieu's suggestion, use general framework to support dump functionality. * Changed to use perf to analyse trace data. Leo Yan (4): coresight: Support panic dump functionality coresight: Add and delete dump node for registration/unregistration coresight: tmc: Hook panic dump callback for ETB/ETF coresight: etm4x: Hook panic dump callback for etmv4 drivers/hwtracing/coresight/Kconfig | 9 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-etm4x.c | 22 +++ drivers/hwtracing/coresight/coresight-etm4x.h | 15 ++ drivers/hwtracing/coresight/coresight-panic-dump.c | 211 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 17 ++ drivers/hwtracing/coresight/coresight-tmc-etf.c | 29 +++ drivers/hwtracing/coresight/coresight.c | 7 + include/linux/coresight.h | 7 + 9 files changed, 318 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-panic-dump.c -- 2.7.4

7 years

[PATCH 0/2] perf inject branch stack fixes

by Robert Walker

These patches fix some issues with the branch stacks generated from CoreSight ETM trace. The main issues addressed are: - The branch stack should only contain taken branches. - The instruction samples are generated using the period specified by the --itrace option to perf inject. Currently, the period can only be specified as an instruction count - further work is required to specify the period as a cycle count or time interval. - The ordering of the branch stack should have newest branch first. - Some minor fixes to the address calculations. With these fixes, the branch stacks are more similar to the last branch records produced by 'perf record -b' and Intel-PT on x86. There are similar improvements in the autofdo profiles generated from these traces. The patches apply to the autoFDO branch of https://github.com/Linaro/perf-opencsd.git (d3fa0f7) Regards Robert Walker Robert Walker (2): Revert "perf inject: record branches in chronological order" perf: Fix branch stack records from CoreSight ETM decode tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 4 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 2 +- tools/perf/util/cs-etm.c | 134 +++++++++++++----------- 3 files changed, 73 insertions(+), 67 deletions(-) -- 1.9.1

7 years, 1 month

[PATCH RFCv1] Crash: Extensions: Coresight panic dump

by Leo Yan

This commit is to add support Coresight panic dump, it uses coresight dump list head pointer to iterate coresight devices; if the device is etm device then use the dump as meta data and use etf device as trace data. It also generates 'perf' format compatible file so the trace data can be analyzed by 'perf' tool. This initial version has limitation: - It can only generate data for etm and etf; haven't verified for other coresight topology; - It can only support etm/etf for N:1 relationship, haven't verified for the device with multiple sink devices. The building and usage are simple, for building can place csdump.c file into 'extensions' folder, then use 'make extensions' to build code, we can get one file name csdump.so. Then we can use csdump.so in 'crash' tool to extract trace files: crash> extend csdump.so crash> csdump trace_out_dir Can use 'extend -u' command to unload the module: crash> extend -u csdump.so Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- extensions/csdump.c | 547 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 547 insertions(+) create mode 100644 extensions/csdump.c diff --git a/extensions/csdump.c b/extensions/csdump.c new file mode 100644 index 0000000..c657378 --- /dev/null +++ b/extensions/csdump.c @@ -0,0 +1,547 @@ +/* + * Extension module to dump log buffer of ARM Coresight Trace + * + * Copyright (C) 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define _GNU_SOURCE +#include <sys/file.h> + +#include "defs.h" + +static unsigned int perf_header[] = { + 0x46524550, 0x32454c49, /* Magic: PERFILE2 */ + 0x00000068, 0x00000000, /* header size */ + 0x00000080, 0x00000000, /* attr size */ + 0x00000078, 0x00000000, /* attrs offset */ + 0x00000100, 0x00000000, /* attrs size */ + 0x00000178, 0x00000000, /* data offset */ + 0x00002568, 0x00000000, /* data size */ + 0x00000000, 0x00000000, /* event offset */ + 0x00000000, 0x00000000, /* event size */ + 0x00040004, 0x00000000, /* feature bitmap */ + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000 +}; + +static unsigned int perf_event_id[] = { + 0x00000015, 0x00000000, + 0x00000016, 0x00000000, +}; + +static unsigned int perf_event_cs_etm[] = { + 0x00000006, 0x00000070, /* event type: 6, size: 0x70 */ + 0x00000000, 0x00000000, /* config: 0 */ + 0x00000001, 0x00000000, /* sample_period: 1 */ + 0x00010003, 0x00000000, /* sample_type: PERF_SAMPLE_IP | PERF_SAMPLE_TID | + PERF_SAMPLE_PERIOD */ + 0x00000004, 0x00000000, /* read_format: PERF_FORMAT_ID */ + 0x00141001, 0x00000000, /* disabled: 1, enable_on_exec: 1, + sample_id_all: 1, exclude_guest: 1 */ + 0x00000000, 0x00000000, /* wakeup_events: 0, bp_type: 0 */ + 0x00000000, 0x00000000, /* config1 : 0 */ + 0x00000000, 0x00000000, /* config1 : 0 */ + 0x00000000, 0x00000000, /* branch_sample_type: 0 */ + 0x00000000, 0x00000000, /* sample_regs_user: 0 */ + 0x00000000, 0x00000000, /* sample_stack_user: 0, clockid: 0 */ + 0x00000000, 0x00000000, /* sample_regs_intr: 0 */ + 0x00000000, 0x00000000, /* aux_watermark: 0, sample_max_stack: 0 */ + 0x00000068, 0x00000000, /* ids.offset: 0x68 */ + 0x00000008, 0x00000000, /* ids.size: 0x8 */ +}; + +static unsigned int perf_event_dummy[] = { + 0x00000001, 0x00000070, /* event type: 1, size: 0x70 */ + 0x00000009, 0x00000000, /* config: 9 */ + 0x00000001, 0x00000000, /* sample_period: 1 */ + 0x00010003, 0x00000000, /* sample_type: PERF_SAMPLE_IP | PERF_SAMPLE_TID | + PERF_SAMPLE_PERIOD */ + 0x00000004, 0x00000000, /* read_format: PERF_FORMAT_ID */ + 0x01843361, 0x00000000, /* disabled: 1, exclude_kernel: 1 + exclude_hv: 1, mmap: 1, + comm: 1, enable_on_exec: 1, + task: 1, sample_id_all: 1, + mmap2: 1, comm_exec: 1 */ + 0x00000000, 0x00000000, /* wakeup_events: 0, bp_type: 0 */ + 0x00000000, 0x00000000, /* config1 : 0 */ + 0x00000000, 0x00000000, /* config1 : 0 */ + 0x00000000, 0x00000000, /* branch_sample_type: 0 */ + 0x00000000, 0x00000000, /* sample_regs_user: 0 */ + 0x00000000, 0x00000000, /* sample_stack_user: 0, clockid: 0 */ + 0x00000000, 0x00000000, /* sample_regs_intr: 0 */ + 0x00000000, 0x00000000, /* aux_watermark: 0, sample_max_stack: 0 */ + 0x00000070, 0x00000000, /* ids.offset: 0x70 */ + 0x00000008, 0x00000000, /* ids.size: 0x8 */ +}; + +static unsigned int perf_auxtrace_info[] = { + 0x00000046, 0x02680000, /* type: PERF_RECORD_AUXTRACE_INFO, size: 0x268 */ + 0x00000003, 0x00000000, /* info->type: PERF_AUXTRACE_CS_ETM */ + 0x00000000, 0x00000000, /* version: 0 */ + 0x00000008, 0x00000006, /* cpus: 8, type: 6 */ + 0x00000000, 0x00000000 /* snapshot_mode: 0 */ +}; + +static unsigned int perf_kernel_mmap[] = { + 0x00000001, 0x00500001, /* type: PERF_RECORD_MMAP, size: 0x50, + misc: PERF_RECORD_MISC_KERNEL */ + 0xffffffff, 0x00000000, /* pid: 0xffffffff, tid: 0x0 */ + 0x08080000, 0xffff0000, /* start: 0xffff000008080000 */ + 0xf7f7ffff, 0x0000ffff, /* len: 0x0000fffff7f7ffff */ + 0x08080000, 0xffff0000, /* pgoff: 0xffff000008080000 */ + 0x72656b5b, 0x2e6c656e, /* filename: [kernel.kallsyms]_text */ + 0x6c6c616b, 0x736d7973, + 0x65745f5d, 0x00007478, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static unsigned int perf_threads[] = { + 0x00000003, 0x00280000, /* type: PERF_RECORD_COMM, size: 0x28 */ + 0x0000090c, 0x0000090c, /* pid: 0x90c, tid: 0x90c */ + 0x66726570, 0x00000000, /* comm: perf */ + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + + 0x00000003, 0x00282000, /* type: PERF_RECORD_COMM, size: 0x28 */ + 0x0000090c, 0x0000090c, /* pid: 0x90c, tid: 0x90c */ + 0x696e6170, 0x00000063, /* comm: panic */ + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, + + 0x0000000a, 0x00680002, /* type: PERF_RECORD_MMAP2, size: 0x68 */ + 0x0000090c, 0x0000090c, /* pid: 0x90c, tid: 0x90c */ + 0x00400000, 0x00000000, /* addr: 0x00400000 */ + 0x00006000, 0x00000000, /* len: 0x00006000 */ + 0x00000000, 0x00000000, /* pgoff: 0x0 */ + 0x000000b3, 0x00000009, /* maj: 0xb3, min: 0x9 */ + 0x00000085, 0x00000000, /* ino: 0x85 */ + 0x00000000, 0x00000000, /* ino_generation: 0x0 */ + 0x00000005, 0x00001802, /* prot: PROT_READ | PROT_EXEC, flag: 0x1802 */ + 0x6e69622f, 0x616e752f, /* comm: /bin/uname */ + 0x0000656d, 0x00000000, + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, + + 0x0000000a, 0x00800002, + 0x0000090c, 0x0000090c, + 0xb77c2000, 0x0000ffff, + 0x0002e000, 0x00000000, + 0x00000000, 0x00000000, + 0x000000b3, 0x00000009, + 0x00000752, 0x00000000, + 0x00000000, 0x00000000, + 0x00000005, 0x00001802, + 0x62696c2f, 0x7261612f, /* ld-2.19.so */ + 0x34366863, 0x6e696c2d, + 0x672d7875, 0x6c2f756e, + 0x2e322d64, 0x732e3931, + 0x0000006f, 0x00000000, + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, + + 0x0000000a, 0x00600002, + 0x0000090c, 0x0000090c, + 0xb77ec000, 0x0000ffff, + 0x00001000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000005, 0x00001002, + 0x7364765b, 0x00005d6f, /* [vdso] */ + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, + + 0x0000000a, 0x00800002, + 0x0000090c, 0x0000090c, + 0xb7675000, 0x0000ffff, + 0x0014d000, 0x00000000, + 0x00000000, 0x00000000, + 0x000000b3, 0x00000009, + 0x0000076a, 0x00000000, + 0x00000000, 0x00000000, + 0x00000005, 0x00001002, + 0x62696c2f, 0x7261612f, /* /lib/aarch64-linux-gnu/libc-2.19.so */ + 0x34366863, 0x6e696c2d, + 0x672d7875, 0x6c2f756e, + 0x2d636269, 0x39312e32, + 0x006f732e, 0x00000000, + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, + + 0x0000000b, 0x00300000, /* type: PERF_RECORD_AUX, size: 0x30 */ + 0x00000000, 0x00000000, /* aux_offset: 0x0 */ + 0x00002000, 0x00000000, /* aux_size: 0x2000 */ + 0x00000001, 0x00000000, /* flag: 0x1 */ + 0x0000090c, 0x0000090c, + 0x00000015, 0x00000000, + + 0x00000004, 0x00300000, /* type: PERF_RECORD_EXIT, size: 0x30 */ + 0x0000090c, 0x0000090c, /* pid, ppid: 0x90c */ + 0x0000090c, 0x0000090c, /* tid, ptid: 0x90c */ + 0xf89cbddc, 0x00000571, + 0x0000090c, 0x0000090c, + 0x00000016, 0x00000000, +}; + +static unsigned int perf_auxtrace_snapshot[] = { + 0x00000047, 0x00300000, /* type: PERF_RECORD_AUXTRACE, size: 0x30 */ + 0x00002000, 0x00000000, /* auxsize: 0x2000 */ + 0x00000000, 0x00000000, /* auxoffset: 0x0 */ + 0x74bc6ab4, 0x5a1c47b3, /* reference: rand() */ + 0x00000000, 0x0000090c, /* idx: 0x0, pid: 0x90c */ + 0xffffffff, 0x00000000, /* cpu: -1 */ +}; + +static unsigned int perf_record_finish[] = { + 0x00000044, 0x00080000, +}; + +static unsigned int perf_sections[] = { + 0x00002760, 0x00000000, /* buildid section: start addr */ + 0x00000064, 0x00000000, /* buildid section: len */ + 0x000027c4, 0x00000000, /* auxtrace section: start addr */ + 0x00000018, 0x00000000, /* auxtrace section: len */ + 0x000027dc, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static unsigned int perf_sections_feat[] = { + 0x00000000, 0x00640001, + 0xffffffff, 0xc9b5ee32, + 0xa6009dc9, 0xcb21093d, + 0x23c315d8, 0x1067c385, + 0x00000000, 0x72656b5b, + 0x2e6c656e, 0x6c6c616b, + 0x736d7973, 0x0000005d, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000000, + + 0x00000001, 0x00000000, + 0x000006a8, 0x00000000, + 0x00000030, 0x00000000, +}; + +#define koffset(struct, member) struct##_##member##_offset + +/* at = ((struct *)ptr)->member */ +#define read_value(at, ptr, struct, member) \ + do { \ + readmem(ptr + koffset(struct, member), KVADDR, \ + &at, sizeof(at), #struct "'s " #member, \ + RETURN_ON_ERROR); \ + } while (0) + + +#define init_offset(struct, member) do { \ + koffset(struct, member) = MEMBER_OFFSET(#struct, #member);\ + if (koffset(struct, member) < 0) { \ + fprintf(fp, "failed to init the offset, struct:"\ + #struct ", member:" #member); \ + fprintf(fp, "\n"); \ + return -1; \ + } \ + } while (0) + +static int koffset(coresight_dump_node, cpu); +static int koffset(coresight_dump_node, list); +static int koffset(coresight_dump_node, buf); +static int koffset(coresight_dump_node, buf_size); +static int koffset(coresight_dump_node, name); +static int koffset(coresight_dump_node, csdev); + +static int koffset(coresight_device, dev); +static int koffset(device, kobj); +static int koffset(kobject, name); + +static struct list_data list_data; +static int instance_count; +static int csdump_metadata_len = 0; + +static int csdump_write_buf(FILE *out_fp, char *component, int cpu_idx) +{ + ulong instance_ptr; + ulong field; + ulong buf_addr; + ulong csdev_addr; + ulong dev_addr; + ulong kobj_addr; + ulong name_addr; + int cpu, buf_sz, i, ret; + char name[64]; + char *buf; + + /* We start i at 1 to skip over the list_head and continue to the last + * instance, which lies at index instance_count */ + for (i = 1; i <= instance_count; i++) { + instance_ptr = list_data.list_ptr[i]; + + field = instance_ptr - koffset(coresight_dump_node, list); + + read_value(cpu, field, coresight_dump_node, cpu); + read_value(buf_addr, field, coresight_dump_node, buf); + read_value(buf_sz, field, coresight_dump_node, buf_size); + + read_value(csdev_addr, field, coresight_dump_node, csdev); + dev_addr = csdev_addr + koffset(coresight_device, dev); + kobj_addr = dev_addr + koffset(device, kobj); + + read_value(name_addr, kobj_addr, kobject, name); + read_string(name_addr, name, 64); + + if (!buf_sz) + continue; + + if (strstr(name, component) && (cpu == cpu_idx)) + break; + } + + if (i > instance_count) + return -1; + + buf = malloc(buf_sz); + readmem(buf_addr, KVADDR, buf, buf_sz, "read dump log buf", + FAULT_ON_ERROR); + + ret = fwrite(buf, buf_sz, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return -1; + } + + free(buf); + + return buf_sz; +} + +static int csdump_metadata(void) +{ + FILE *out_fp; + int online_cpus, i; + + if ((out_fp = fopen("./metadata.bin", "w")) == NULL) { + fprintf(fp, "Cannot open file\n"); + return -1; + } + + online_cpus = get_cpus_online(); + for (i = 0; i < online_cpus; i++) { + fprintf(fp, "cpu = %d\n", i); + csdump_metadata_len += csdump_write_buf(out_fp, "etm", i); + } + + fclose(out_fp); + + return 0; +} + +static int csdump_tracedata(void) +{ + FILE *out_fp; + + if ((out_fp = fopen("./cstrace.bin", "w")) == NULL) { + fprintf(fp, "Cannot open file\n"); + return -1; + } + + csdump_write_buf(out_fp, "etf", 0); + + fclose(out_fp); + + return 0; +} + +static int csdump_perfdata(void) +{ + FILE *out_fp; + int online_cpus, i; + int trace_len = 0; + int pos, diff; + + if ((out_fp = fopen("./perf.data", "w")) == NULL) { + fprintf(fp, "Cannot open file\n"); + return -1; + } + + fwrite(perf_header, sizeof(perf_header), 1, out_fp); + fwrite(perf_event_id, sizeof(perf_event_id), 1, out_fp); + fwrite(perf_event_cs_etm, sizeof(perf_event_cs_etm), 1, out_fp); + fwrite(perf_event_dummy, sizeof(perf_event_dummy), 1, out_fp); + + online_cpus = get_cpus_online(); + + /* Adjust auxtrace_info size */ + perf_auxtrace_info[1] = (perf_auxtrace_info[1] & 0xffff) | + ((sizeof(perf_auxtrace_info) + csdump_metadata_len) << 16); + /* Adjust CPU num */ + perf_auxtrace_info[6] = online_cpus; + + fwrite(perf_auxtrace_info, sizeof(perf_auxtrace_info), 1, out_fp); + trace_len += sizeof(perf_auxtrace_info); + + for (i = 0; i < online_cpus; i++) { + fprintf(fp, "cpu = %d\n", i); + trace_len += csdump_write_buf(out_fp, "etm", i); + } + + fwrite(perf_kernel_mmap, sizeof(perf_kernel_mmap), 1, out_fp); + trace_len += sizeof(perf_kernel_mmap); + + fwrite(perf_threads, sizeof(perf_threads), 1, out_fp); + trace_len += sizeof(perf_threads); + + fwrite(perf_auxtrace_snapshot, sizeof(perf_auxtrace_snapshot), 1, out_fp); + trace_len += sizeof(perf_auxtrace_snapshot); + + trace_len += csdump_write_buf(out_fp, "etf", 0); + + fwrite(perf_record_finish, sizeof(perf_record_finish), 1, out_fp); + trace_len += sizeof(perf_record_finish); + + pos = ftell(out_fp); + pos += sizeof(perf_sections); + + diff = perf_sections[0] - pos; + + for (i = 0; i < sizeof(perf_sections) / 4; i += 4) { + if (!perf_sections[i]) + continue; + + perf_sections[i] = perf_sections[i] - diff; + } + + fwrite(perf_sections, sizeof(perf_sections), 1, out_fp); + fwrite(perf_sections_feat, sizeof(perf_sections_feat), 1, out_fp); + + fseek(out_fp, 48L, SEEK_SET); + fwrite(&trace_len, sizeof(trace_len), 1, out_fp); + + fclose(out_fp); + + return 0; +} + +static int csdump_prepare(void) +{ + struct syment *sym_dump_list; + struct kernel_list_head *cs_dump_list_head; + + init_offset(coresight_dump_node, cpu); + init_offset(coresight_dump_node, list); + init_offset(coresight_dump_node, buf); + init_offset(coresight_dump_node, buf_size); + init_offset(coresight_dump_node, name); + init_offset(coresight_dump_node, csdev); + + init_offset(coresight_device, dev); + init_offset(device, kobj); + init_offset(kobject, name); + + /* Get pointer to dump list */ + sym_dump_list = symbol_search("coresight_dump_list"); + if (!sym_dump_list) { + fprintf(fp, "symbol coresight_dump_list is not found\n"); + return -1; + } + + cs_dump_list_head = (void *)sym_dump_list->value; + fprintf(fp, "cs_dump_list_head = 0x%p\n", cs_dump_list_head); + + BZERO(&list_data, sizeof(struct list_data)); + list_data.start = (ulong)cs_dump_list_head; + list_data.end = (ulong)cs_dump_list_head; + list_data.flags = LIST_ALLOCATE; + instance_count = do_list(&list_data); + + /* + * The do_list count includes the list_head, which is not + * a proper instance so minus 1. + */ + instance_count--; + if (instance_count <= 0) + return -1; + + return 0; +} + +static void csdump_unprepare(void) +{ + FREEBUF(list_data.list_ptr); +} + +void cmd_csdump(void) +{ + char* outdir; + mode_t mode = S_IRUSR | S_IWUSR | S_IXUSR | + S_IRGRP | S_IXGRP | + S_IROTH | S_IXOTH; /* 0755 */ + int ret; + + if (argcnt != 2) + cmd_usage(pc->curcmd, SYNOPSIS); + + outdir = args[1]; + if ((ret = mkdir(outdir, mode))) { + fprintf(fp, "Cannot create directory %s: %d\n", outdir, ret); + return; + } + + if ((ret = chdir(outdir))) { + fprintf(fp, "Cannot chdir %s: %d\n", outdir, ret); + return; + } + + if (csdump_prepare()) + goto out; + + csdump_metadata(); + csdump_tracedata(); + csdump_perfdata(); + +out: + csdump_unprepare(); + chdir(".."); + return; +} + +char *help_csdump[] = { + "csdump", + "Dump log buffer of Coresight Trace", + "<output-dir>", + "This command extracts coresight log buffer to the directory", + "specified by <output-dir>", + NULL +}; + +static struct command_table_entry command_table[] = { + { "csdump", cmd_csdump, help_csdump, 0}, + { NULL }, +}; + +void __attribute__((constructor)) +csdump_init(void) +{ + register_extension(command_table); +} + +void __attribute__((destructor)) +csdump_fini(void) { } -- 2.7.4

7 years, 1 month

[PATCH 00/17] coresight: perf: TMC ETR backend support

by Suzuki K Poulose

The TMC-ETR supports routing the Coresight trace data to the System memory. It supports two different modes in which the memory could be used. 1) Contiguous memory - The memory is assumed to be physically contiguous. 2) Scatter Gather list - The memory can be chunks of 4K pages, which are specified in a table of pointers which itself could be multiple 4K size pages. To avoid the complications of the managing the buffer, this series adds a layer for managing the ETR buffer, which makes the best possibly choice based on what is available. The allocation can be tuned by passing in flags, existing pages (e.g, perf ring buffer) etc. Towards supporting ETR Scatter Gather mode, we introduce a generic TMC scatter-gather table which can be used to manage the data and table pages. The table can be filled in the format expected by the Scatter-Gather mode. The TMC ETR-SG mechanism doesn't allow starting the trace at non-zero offset (required by perf). So we make some tricky changes to the table at run time to allow starting at any "Page aligned" offset and then wrap around to the beginning of the buffer with very less overhead. See patches for more description. The series also improves the way the ETR is controlled by different modes (sysfs vs. perf) by keeping mode specific data. This allows access to the trace data collected in sysfs mode, even when the ETR is operated in perf mode. Also with the transparent management of the buffer and scatter-gather mechanism, we can allow the user to request for larger trace buffers for sysfs mode. This is supported by providing a sysfs file, "buffer_size" which accepts a page aligned size, which will be used by the ETR when allocating a buffer. Finally, it cleans up the etm perf sink callbacks a little bit and then adds the support for ETR sink. For the ETR, we try our best to use the perf ring buffer as the target hardware buffer, provided : 1) The ETR is dma coherent (since the pages will be shared with userspace perf tool). 2) The perf is used in snapshot mode (The ETR cannot be stopped based on the size of the data written hence we could easily overwrite the buffer. We may be able to fix this in the future) 3) The ETR supports the Scatter-Gather mode. If we can't use the perf buffers directly, we fallback to using software buffering where we have to copy the trace data back to the perf ring buffer. Suzuki K Poulose (17): coresight etr: Disallow perf mode temporarily coresight tmc: Hide trace buffer handling for file read coresight: Add helper for inserting synchronization packets coresight: Add generic TMC sg table framework coresight: Add support for TMC ETR SG unit coresight: tmc: Make ETR SG table circular coresight: tmc etr: Add transparent buffer management coresight: tmc: Add configuration support for trace buffer size coresight: Convert driver messages to dev_dbg coresight: etr: Track if the device is coherent coresight etr: Handle driver mode specific ETR buffers coresight etr: Relax collection of trace from sysfs mode coresight etr: Do not clean ETR trace buffer coresight: etr: Add support for save restore buffers coresight: etr_buf: Add helper for padding an area of trace data coresight: perf: Remove reset_buffer call back for sinks coresight perf: Add ETR backend support for etm-perf .../ABI/testing/sysfs-bus-coresight-devices-tmc | 8 + .../coresight/coresight-dynamic-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-etb10.c | 72 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 9 +- drivers/hwtracing/coresight/coresight-etm3x.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x.c | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 4 +- drivers/hwtracing/coresight/coresight-priv.h | 8 + drivers/hwtracing/coresight/coresight-replicator.c | 4 +- drivers/hwtracing/coresight/coresight-stm.c | 4 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 109 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 1665 ++++++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc.c | 75 +- drivers/hwtracing/coresight/coresight-tmc.h | 128 +- drivers/hwtracing/coresight/coresight-tpiu.c | 4 +- include/linux/coresight.h | 5 +- 16 files changed, 1837 insertions(+), 270 deletions(-) -- 2.13.6

7 years, 1 month

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CoreSight November 2017