This series enables future IP trace features Embedded Trace Extension (ETE)
and Trace Buffer Extension (TRBE). This series depends on the ETM system
register instruction support series [0] and the v8.4 Self hosted tracing
support series (Jonathan Zhou) [1]. The tree is available here [2] for
quick access.
ETE is the PE (CPU) trace unit for CPUs, implementing future architecture
extensions. ETE overlaps with the ETMv4 architecture, with additions to
support the newer architecture features and some restrictions on the
supported features w.r.t ETMv4. The ETE support is added by extending the
ETMv4 driver to recognise the ETE and handle the features as exposed by the
TRCIDRx registers. ETE only supports system instructions access from the
host CPU. The ETE could be integrated with a TRBE (see below), or with the
legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware
description as the ETMs and requires a node per instance.
Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is
accessible via the system registers and can be combined with the ETE to
provide a 1x1 configuration of source & sink. TRBE is being represented
here as a CoreSight sink. Primary reason is that the ETE source could work
with other traditional CoreSight sink devices. As TRBE captures the trace
data which is produced by ETE, it cannot work alone.
TRBE representation here have some distinct deviations from a traditional
CoreSight sink device. Coresight path between ETE and TRBE are not built
during boot looking at respective DT or ACPI entries. Instead TRBE gets
checked on each available CPU, when found gets connected with respective
ETE source device on the same CPU, after altering its outward connections.
ETE TRBE path connection lasts only till the CPU is online. But ETE-TRBE
coupling/decoupling method implemented here is not optimal and would be
reworked later on.
Unlike traditional sinks, TRBE can generate interrupts to signal including
many other things, buffer got filled. The interrupt is a PPI and should be
communicated from the platform. DT or ACPI entry representing TRBE should
have the PPI number for a given platform. During perf session, the TRBE IRQ
handler should capture trace for perf auxiliary buffer before restarting it
back. System registers being used here to configure ETE and TRBE could be
referred in the link below.
https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.
This adds another change where CoreSight sink device needs to be disabled
before capturing the trace data for perf in order to avoid race condition
with another simultaneous TRBE IRQ handling. This might cause problem with
traditional sink devices which can be operated in both sysfs and perf mode.
This needs to be addressed correctly. One option would be to move the
update_buffer callback into the respective sink devices. e.g, disable().
This series is primarily looking from some early feed back both on proposed
design and its implementation. It acknowledges, that it might be incomplete
and will have scopes for improvement.
Things todo:
- Improve ETE-TRBE coupling and decoupling method
- Improve TRBE IRQ handling for all possible corner cases
- Implement sysfs based trace sessions
[0] https://lore.kernel.org/linux-arm-kernel/20201028220945.3826358-1-suzuki.po…
[1] https://lore.kernel.org/linux-arm-kernel/1600396210-54196-1-git-send-email-…
[2] https://gitlab.arm.com/linux-arm/linux-skp/-/tree/coresight/etm/v8.4-self-h…
Anshuman Khandual (6):
arm64: Add TRBE definitions
coresight: sink: Add TRBE driver
coresight: etm-perf: Truncate the perf record if handle has no space
coresight: etm-perf: Disable the path before capturing the trace data
coresgith: etm-perf: Connect TRBE sink with ETE source
dts: bindings: Document device tree binding for Arm TRBE
Suzuki K Poulose (5):
coresight: etm-perf: Allow an event to use different sinks
coresight: Do not scan for graph if none is present
coresight: etm4x: Add support for PE OS lock
coresight: ete: Add support for sysreg support
coresight: ete: Detect ETE as one of the supported ETMs
.../devicetree/bindings/arm/coresight.txt | 3 +
Documentation/devicetree/bindings/arm/trbe.txt | 20 +
Documentation/trace/coresight/coresight-trbe.rst | 36 +
arch/arm64/include/asm/sysreg.h | 51 ++
drivers/hwtracing/coresight/Kconfig | 11 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-etm-perf.c | 85 ++-
drivers/hwtracing/coresight/coresight-etm-perf.h | 4 +
drivers/hwtracing/coresight/coresight-etm4x-core.c | 144 +++-
drivers/hwtracing/coresight/coresight-etm4x.h | 64 +-
drivers/hwtracing/coresight/coresight-platform.c | 9 +-
drivers/hwtracing/coresight/coresight-trbe.c | 768 +++++++++++++++++++++
drivers/hwtracing/coresight/coresight-trbe.h | 525 ++++++++++++++
include/linux/coresight.h | 2 +
14 files changed, 1680 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
create mode 100644 Documentation/trace/coresight/coresight-trbe.rst
create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c
create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h
--
2.7.4
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Hi all,
[ + CoreSight Mailing List ]
On the mainlne kernel with the latest commit 407ab579637c
"Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm",
the perf cs-etm testing fails.
I found the perf cs-etm testing itself has a typo issue and a regression
introduced by Perf tool in the recent mainline kernel, so I sent out the
two patches for fixing the related issues [1].
Even after applying these two fixings for the testing script, I still
observe the etm testing failure with snapshot mode. I manully checked
the perf data and confirmed the perf data contains the raw trace data
for snapshot (so 'perf script -D' can work well), but it fails to
generate any branch samples, so the command 'perf script' will not
output any samples.
Seems to me, this issue is more likely related with driver or Perf
tool's common code change but not the testing itself; Before I proceed
to use 'git bisect' to narrow down the snapshot mode failure, if you
have any idea for fixing this issue, please let me know. Otherwise, I
will dig into this issue and keep posted.
Thanks,
Leo
[1] https://lore.kernel.org/patchwork/patch/1336053/
__always_inline can cause build error on musl libc. The fix patch has
submitted but not merged yet[1]. To build perf tool with musl libc,
<linux/stddef.h> inclusion is necessary and it should be included before
perf_event.h.
from /usr/include/linux/byteorder/little_endian.h:13,
from /usr/include/asm/byteorder.h:23,
from tools/include/uapi/linux/perf_event.h:20,
from arch/arm64/util/../../arm/util/pmu.c:9:
/usr/include/linux/swab.h:171:8: error: unknown type name '__always_inline'
171 | static __always_inline __u16 __swab16p(const __u16 *p)
| ^~~~~~~~~~~~~~~
[1]: https://lkml.org/lkml/2018/9/13/78
Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com>
Cc: Mike Leach <mike.leach(a)linaro.org>
Cc: Leo Yan <leo.yan(a)linaro.org>
Cc: John Garry <john.garry(a)huawei.com>
Cc: Will Deacon <will(a)kernel.org>
Cc: Peter Zijlstra <peterz(a)infradead.org>
Cc: Ingo Molnar <mingo(a)redhat.com>
Cc: Arnaldo Carvalho de Melo <acme(a)kernel.org>
Cc: Mark Rutland <mark.rutland(a)arm.com>
Cc: Jiri Olsa <jolsa(a)redhat.com>
Cc: Namhyung Kim <namhyung(a)kernel.org>
Cc: Khem Raj <raj.khem(a)gmail.com>
Signed-off-by: Chanho Park <chanho61.park(a)samsung.com>
---
tools/perf/arch/arm/util/pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
index bbc297a7e2e3..4c0357e8c0ab 100644
--- a/tools/perf/arch/arm/util/pmu.c
+++ b/tools/perf/arch/arm/util/pmu.c
@@ -6,6 +6,9 @@
#include <string.h>
#include <linux/coresight-pmu.h>
+#if !defined(__GLIBC__)
+#include <linux/stddef.h>
+#endif
#include <linux/perf_event.h>
#include <linux/string.h>
--
2.23.0