CoreSight October 2021

coresight@lists.linaro.org

8 participants
36 discussions

Re: [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures

by Suzuki K Poulose

On 11/10/2021 11:18, Will Deacon wrote: > On Fri, Oct 08, 2021 at 07:29:05PM +0100, Suzuki K Poulose wrote: >> Advertise the workaround for the TSB flush failures via >> Kconfig entries. >> >> Cc: Will Deacon <will(a)kernel.org> >> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Marc Zyngier <maz(a)kernel.org> >> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Acked-by: Catalin Marinas <catalin.marinas(a)arm.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> Changes since previous: >> - Split the Kconfig/erratum updates to keep the conflicts >> minimal with the other Kconfig updates in TRBE errata >> I have retained the tags >> --- >> Documentation/arm64/silicon-errata.rst | 4 ++++ >> arch/arm64/Kconfig | 31 ++++++++++++++++++++++++++ >> 2 files changed, 35 insertions(+) >> >> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >> index 2f99229d993c..569a92411dcd 100644 >> --- a/Documentation/arm64/silicon-errata.rst >> +++ b/Documentation/arm64/silicon-errata.rst >> @@ -94,6 +94,8 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1349291 | N/A | >> @@ -102,6 +104,8 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | MMU-500 | #841119,826419 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> +----------------+-----------------+-----------------+-----------------------------+ >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index eac4030322df..0764774e12bb 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -705,6 +705,37 @@ config ARM64_ERRATUM_2139208 >> >> If unsure, say Y. >> >> +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> + bool >> + >> +config ARM64_ERRATUM_2054223 >> + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" >> + default y >> + help >> + Enable workaround for ARM Cortex-A710 erratum 2054223 >> + >> + Affected cores may fail to flush the trace data on a TSB instruction, when >> + the PE is in trace prohibited state. This will cause losing a few bytes >> + of the trace cached. >> + >> + Workaround is to issue two TSB consecutively on affected cores. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2067961 >> + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" >> + default y >> + help >> + Enable workaround for ARM Neoverse-N2 erratum 2067961 >> + >> + Affected cores may fail to flush the trace data on a TSB instruction, when >> + the PE is in trace prohibited state. This will cause losing a few bytes >> + of the trace cached. >> + >> + Workaround is to issue two TSB consecutively on affected cores. >> + >> + If unsure, say Y. > > Shouldn't these two be selecting the workaround? doh! I have given myself a slap for this and fixed it locally. Suzuki

2 years, 6 months

[PATCH v3 00/16] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. All Kconfig changes are at the end of the series and could go via the coresight tree to make sure that the work arounds are available in the final tree before they can be selected by the user. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v3 Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (16): for arm64 tree arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range for CoreSight tree coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Advertise workaround for TRBE overwrite in FILL mode arm64: errata: Advertise the workaround for TSB flush failures arm64: errata: Advertise TRBE erratum workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 109 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 382 +++++++++++++++++-- 7 files changed, 554 insertions(+), 36 deletions(-) -- 2.25.4

2 years, 6 months

Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

On 08/10/2021 10:52, Will Deacon wrote: > On Fri, Oct 08, 2021 at 10:25:03AM +0100, Suzuki K Poulose wrote: >> Hi Will >> >> On 08/10/2021 08:32, Will Deacon wrote: >>> Hi Suzuki, >>> >>> On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote: >>>> This series adds CPU erratum work arounds related to the self-hosted >>>> tracing. The list of affected errata handled in this series are : >>>> >>>> * TRBE may overwrite trace in FILL mode >>>> - Arm Neoverse-N2 #2139208 >>>> - Cortex-A710 #211985 >>>> >>>> * A TSB instruction may not flush the trace completely when executed >>>> in trace prohibited region. >>>> >>>> - Arm Neoverse-N2 #2067961 >>>> - Cortex-A710 #2054223 >>>> >>>> * TRBE may write to out-of-range address >>>> - Arm Neoverse-N2 #2253138 >>>> - Cortex-A710 #2224489 >>>> >>>> The series applies on the self-hosted/trbe fixes posted here [0]. >>>> A tree containing both the series is available here [1] >>> >>> Any chance you could put the arch/arm64/ bits at the start of the series, >>> please? That way, I can queue them on their own branch which can be shared >>> with the coresight tree. >> >> I could move the bits around. I have a question though. >> >> Will, Catalin, Mathieu, >> >> The workaround for these errata, at least two of them are >> in the TRBE driver patches. Are we happy with enabling the Kconfig >> entry in the kernel, without the CoreSight patches to implement the work >> around ? > > I suppose you could move all the Kconfig changes into their own patch and > stick it right at the end in the Coresight tree. Cool, I will do that then. Thanks. I will send the updated series. Suzuki

2 years, 6 months

Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

Hi Will On 08/10/2021 08:32, Will Deacon wrote: > Hi Suzuki, > > On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote: >> This series adds CPU erratum work arounds related to the self-hosted >> tracing. The list of affected errata handled in this series are : >> >> * TRBE may overwrite trace in FILL mode >> - Arm Neoverse-N2 #2139208 >> - Cortex-A710 #211985 >> >> * A TSB instruction may not flush the trace completely when executed >> in trace prohibited region. >> >> - Arm Neoverse-N2 #2067961 >> - Cortex-A710 #2054223 >> >> * TRBE may write to out-of-range address >> - Arm Neoverse-N2 #2253138 >> - Cortex-A710 #2224489 >> >> The series applies on the self-hosted/trbe fixes posted here [0]. >> A tree containing both the series is available here [1] > > Any chance you could put the arch/arm64/ bits at the start of the series, > please? That way, I can queue them on their own branch which can be shared > with the coresight tree. I could move the bits around. I have a question though. Will, Catalin, Mathieu, The workaround for these errata, at least two of them are in the TRBE driver patches. Are we happy with enabling the Kconfig entry in the kernel, without the CoreSight patches to implement the work around ? Suzuki

2 years, 6 months

[PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on the self-hosted/trbe fixes posted here [0]. A tree containing both the series is available here [1] [0] https://lkml.kernel.org/r/20210914102641.1852544-1-suzuki.poulose@arm.com [1] git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v2 Changes since v1: https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (17): coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: Add erratum detection for TRBE overwrite in FILL mode coresight: trbe: Workaround TRBE errata overwrite in FILL mode arm64: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures coresight: trbe: Add a helper to fetch cpudata from perf handle coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space arm64: Add erratum detection for TRBE write to out-of-range coresight: trbe: Work around write to out of range arm64: Advertise TRBE erratum workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 109 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 339 +++++++++++++++++-- 7 files changed, 510 insertions(+), 37 deletions(-) -- 2.24.1

2 years, 6 months

[PATCH v2 00/12] OpenCSD: v1.2.0: Update to add decode statistics API.

by Mike Leach

Adds a generic API to allow packet processors to count the amount of bytes per channel processed and not synced plus any packet header or format errors. The ETMv4 / ETE packet processor is updated to use this API. Statistics are also provided for the CoreSight frame demux, which are global across all channels. Typical output from trc_pkt_lister when run with -stats option to print stats: =============================================================== Trace Packet Lister : Trace buffer done, processed 65536 bytes. Reading packet decoder statistics.... Decode stats ID 0x10 Total Bytes: 55273; Unsynced Bytes: 1453 Bad Header Errors: 0; Bad Sequence Errors: 0 Decode stats ID 0x11 Total Bytes: 672; Unsynced Bytes: 132 Bad Header Errors: 0; Bad Sequence Errors: 0 Decode stats ID 0x12 Total Bytes: 672; Unsynced Bytes: 648 Bad Header Errors: 0; Bad Sequence Errors: 0 Decode stats ID 0x13 Total Bytes: 698; Unsynced Bytes: 0 Bad Header Errors: 0; Bad Sequence Errors: 0 Decode stats ID 0x14 Total Bytes: 0; Unsynced Bytes: 0 Bad Header Errors: 0; Bad Sequence Errors: 0 Decode stats ID 0x15 Total Bytes: 2783; Unsynced Bytes: 471 Bad Header Errors: 0; Bad Sequence Errors: 0 Frame Demux Stats Trace data bytes sent to registered ID decoders: 60098 Trace data bytes without registered ID decoders: 0 Trace data bytes with unknown ID: 81 Trace data bytes with reserved ID: 22 Frame demux bytes, ID bytes and sync bytes: 5335 Total bytes processed by frame demux: 65536 ================================================================ API adds ocsd_decode_stats_t structure to contain the statistics. (ocsd_if_types.h) C-API (ocsd_c_apo.h) adds functions:- ocsd_dt_get_decode_stats() - get pointer to stats block. ocsd_dt_reset_decode_stats() - resets the counts to zero. This function operates independently of the main decoder reset. This allows for tools such as perf which may reset the decoder multiple times per AUXTRACE_BUFFER to count stats for the entire buffer rather than each capture block. Changes since v1: 1) stats structure now contains a block for frame demux data. 2) patchset contains a number of additional build and code fixes that will be included in the 1.2.0 release. James Clark (1): opencsd: Remove noisy printf Mike Leach (10): opencsd: Add decode statistics API to packet processor. opencsd: ETMv4: ETE: Add packet processing stats to decoders. tests: Update test programs to use the packet decoder statistics API build: tests: Fix build warnings in snapshot parser. build: tests: Fix build warnings in mem_buff_demo test build: tests: Fix build warnings in C-API test program opencsd: stats: Add collection of CoreSight frame demux stats tests: Add printing of CS frame Demux stats to test program. tests: Update test scripts to pass additional options opencsd: Update readme and version info for v1.2.0 Yi Kong (1): opencsd: build: Remove unused variable README.md | 9 ++- decoder/include/common/ocsd_dcd_tree.h | 29 ++++++++- .../include/common/trc_frame_deformatter.h | 4 ++ decoder/include/common/trc_pkt_proc_base.h | 47 +++++++++++++- decoder/include/opencsd/c_api/opencsd_c_api.h | 30 ++++++++- decoder/include/opencsd/ocsd_if_types.h | 47 ++++++++++++++ decoder/include/opencsd/ocsd_if_version.h | 6 +- decoder/source/c_api/ocsd_c_api.cpp | 18 +++++- decoder/source/etmv4/trc_pkt_proc_etmv4i.cpp | 10 ++- decoder/source/ocsd_dcd_tree.cpp | 64 +++++++++++++++++++ decoder/source/trc_frame_deformatter.cpp | 60 +++++++++++++++-- decoder/source/trc_frame_deformatter_impl.h | 14 +++- decoder/source/trc_printable_elem.cpp | 2 - decoder/tests/run_pkt_decode_single.bash | 7 +- decoder/tests/run_pkt_decode_tests-ete.bash | 11 ++-- decoder/tests/run_pkt_decode_tests.bash | 17 +++-- .../include/snapshot_parser.h | 6 +- .../source/snapshot_parser.cpp | 4 ++ decoder/tests/source/c_api_pkt_print_test.c | 39 ++++++++++- decoder/tests/source/mem_buff_demo.cpp | 9 ++- decoder/tests/source/trc_pkt_lister.cpp | 63 +++++++++++++++++- 21 files changed, 455 insertions(+), 41 deletions(-) -- 2.17.1

2 years, 6 months

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CoreSight October 2021