On 25/01/2022 03:21, Anshuman Khandual wrote:
>
>
> On 1/11/22 9:08 AM, Anshuman Khandual wrote:
>> This series adds three different workarounds in the TRBE driver for
>> Cortex-A510 specific erratas. But first, this adds Cortex-A510 specific cpu
>> part number definition in the platform. This series applies on 5.16.
>>
>> Relevant errata documents can be found here.
>>
>> https://developer.arm.com/documentation/SDEN2397239/900
>> https://developer.arm.com/documentation/SDEN2397589/900
>>
>> Changes in V3:
>>
>> - Moved the comment inside trbe_needs_drain_after_disable()
>> - Moved the comment inside trbe_needs_ctxt_sync_after_enable()
>>
>> Changes in V2:
>>
>> https://lore.kernel.org/all/1641517808-5735-1-git-send-email-anshuman.khand…
>>
>> Accommodated most review comments from the previous version.
>>
>> - Split all patches into CPU errata definition, detection and TRBE workarounds
>> - s/TRBE_WORKAROUND_SYSREG_WRITE_FAILURE/TRBE_NEEDS_DRAIN_AFTER_DISABLE
>> - s/TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE/TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE
>> - s/trbe_may_fail_sysreg_write()/trbe_needs_drain_after_disable()
>> - s/trbe_may_corrupt_with_enable()/trbe_needs_ctxt_sync_after_enable()
>> - Updated Kconfig help message for config ARM64_ERRATUM_1902691
>> - Updated error message for trbe_is_broken() detection
>> - Added new trblimitr parameter to set_trbe_enabled(), improving performance
>> - Added COMPILE_TEST dependency in the errata, until TRBE part is available
>>
>> Changes in V1:
>>
>> https://lore.kernel.org/lkml/1641359159-22726-1-git-send-email-anshuman.kha…
>>
>> Cc: Catalin Marinas <catalin.marinas(a)arm.com>
>> Cc: Will Deacon <will(a)kernel.org>
>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com>
>> Cc: coresight(a)lists.linaro.org
>> Cc: linux-doc(a)vger.kernel.org
>> Cc: linux-arm-kernel(a)lists.infradead.org
>> Cc: linux-kernel(a)vger.kernel.org
>>
>> Anshuman Khandual (7):
>> arm64: Add Cortex-A510 CPU part definition
>> arm64: errata: Add detection for TRBE ignored system register writes
>> arm64: errata: Add detection for TRBE invalid prohibited states
>> arm64: errata: Add detection for TRBE trace data corruption
>> coresight: trbe: Work around the ignored system register writes
>> coresight: trbe: Work around the invalid prohibited states
>> coresight: trbe: Work around the trace data corruption
>
> Hello Catalin/Mathieu,
>
> I am wondering how this series is going to be merged i.e via arm64 or coresight
> tree ? Also will this require rebasing (and resend) against v5.17-rc1 release.
> Please do suggest. Thank you.
I would recommend rebasing on rc1.
Thanks
Suzuki
Hi Jay,
On Tue, Jan 25, 2022 at 10:33:45AM +0800, Jiankang Chen wrote:
> Hi Mathieu
>
> 在 2022/1/25 04:08, Mathieu Poirier 写道:
> > On Mon, 24 Jan 2022 at 04:00, Jay Chen <jkchen(a)linux.alibaba.com> wrote:
> > > Currently, there are 130 etr and etf on our machine,
> > > but the current coresight tmc driver uses misc_register
> > > to register the device, which leads to the error that
> > > the device number is not enough.
> > >
> > > coresight-tmc: probe of xxxxx failed with error -16
> > >
> > > This patch changes the device registration method
> > > to cdev's dynamic registration method to solve the
> > > problem of insufficient device numbers.
> > This patch is still not labelled properly and as such being dropped.
>
> Hello, about the label of this patch, what kind of patch should I add?
You could use "git format" command with option "-v" to add the version
number, e.g. if you are committing patch version 4, so you can generate
patch like:
$ git format-patch HEAD~1 -v4
Or if you want to generate patch for a specific commit:
$ git format-patch -1 patch_commit -v4
Every time when you generate a new version's patch, you could
increment the version number with option "-v4", "-v5", and so on.
P.s. I strongly suggest Marc Zyngier's great talk for how to upstream
kernel patch in a good way:
https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Getting-You…
Thanks,
Leo
On 24/01/2022 03:15, Anshuman Khandual wrote:
> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
> well. This series updates the errata definition and detection as required.
> This series applies on v5.17-rc1.
>
> Relevant identification document can be found here.
>
> https://developer.arm.com/documentation/101803/0200/AArch64-system-register…
> AArch64-identification-register-summary/MIDR-EL1--Main-ID-Register
>
> Relevant errata document can be found here.
>
> https://developer.arm.com/documentation/SDEN1775100
>
> Cc: Catalin Marinas <catalin.marinas(a)arm.com>
> Cc: Will Deacon <will(a)kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com>
> Cc: coresight(a)lists.linaro.org
> Cc: linux-arm-kernel(a)lists.infradead.org
> Cc: linux-kernel(a)vger.kernel.org
>
For the series:
Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
The kernel uses open code to check if a process is in root PID namespace
or not in several places.
Suggested by Suzuki, this patch set is to create a helper function
task_is_in_init_pid_ns() to replace open code.
This patch set has been applied on the mainline kernel and built for
Arm64 kernel with enabling all relevant modules.
Changes from v1:
* Renamed helper function from task_is_in_root_ns() to
task_is_in_init_pid_ns(). (Leon Romanovsky)
* Improved patches' commit logs for more neat.
Leo Yan (7):
pid: Introduce helper task_is_in_init_pid_ns()
coresight: etm3x: Use task_is_in_init_pid_ns()
coresight: etm4x: Use task_is_in_init_pid_ns()
connector/cn_proc: Use task_is_in_init_pid_ns()
coda: Use task_is_in_init_pid_ns()
audit: Use task_is_in_init_pid_ns()
taskstats: Use task_is_in_init_pid_ns()
drivers/connector/cn_proc.c | 2 +-
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 8 ++++----
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++----
fs/coda/inode.c | 2 +-
fs/coda/psdev.c | 2 +-
include/linux/pid_namespace.h | 5 +++++
kernel/audit.c | 2 +-
kernel/taskstats.c | 2 +-
8 files changed, 18 insertions(+), 13 deletions(-)
--
2.25.1
I was working on refactoring some of the magic numbers for the register
accesses and I saw this issue with programming one of the values.
I don't have any evidence that someone encountered it not working, probably
there is no hardware where QSUPP==0b10, or it just didn't get used yet.
But the issue is that this silently writes a reserved value even if the
user provided one was correct so it might ruin someones day if it ever
comes up.
It's a small change so I didn't see the harm in fixing it.
Applies to coresight/next f9809d565135
James Clark (1):
coresight: Fix TRCCONFIGR.QE sysfs interface
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1