CoreSight March 2022

coresight@lists.linaro.org

10 participants
27 discussions

Re: [PATCH v4 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM

by Jinlong Mao

On 3/24/2022 8:26 PM, Greg Kroah-Hartman wrote: > On Thu, Mar 24, 2022 at 08:17:30PM +0800, Mao Jinlong wrote: >> Add API usage document for sysfs API in TPDM driver. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm | 5 +++++ >> 1 file changed, 5 insertions(+) >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> >> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> new file mode 100644 >> index 000000000000..1df2f9b9ade2 >> --- /dev/null >> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >> @@ -0,0 +1,5 @@ >> +What: /sys/bus/coresight/devices/<tpdm-name>/integration_test >> +Date: February 2022 > It is no longer February. > >> +KernelVersion 5.17 > 5.17 is long past. > >> +Contact: Jinlong Mao or Tao Zhang > How do we contact these names? > >> +Description: (Write) Run integration test for tpdm. > I do not understand this description at all. Please explain it much > better. > > thanks, > > greg k-h Thanks for the review. I will address your comments in next version. Thanks Jinlong Mao

2 years, 9 months

[PATCH v4 00/10] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. Use IDR to maintain all the enabled sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series "coresight: Add new API to allocate trace source ID values". https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220308205000.… Changes from V3: 1. Drop trace id for tpdm source as its trace atid is defined by the tpda. Allocate tpda's atid dynamically. (Mike Leach) Mao Jinlong (10): Use IDR to maintain all the enabled sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 .../testing/sysfs-bus-coresight-devices-tpdm | 5 + .../bindings/arm/coresight-tpda.yaml | 119 +++ .../bindings/arm/coresight-tpdm.yaml | 99 +++ .../devicetree/bindings/arm/coresight.txt | 7 + MAINTAINERS | 1 + .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 708 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 + drivers/hwtracing/coresight/Kconfig | 33 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 79 +- drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++ drivers/hwtracing/coresight/coresight-tpda.h | 32 + drivers/hwtracing/coresight/coresight-tpdm.c | 260 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 56 ++ include/linux/coresight.h | 1 + 15 files changed, 1546 insertions(+), 50 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

2 years, 9 months

Re: [PATCH v2 0/1] perf: Set build-id using build-id header on new mmap records

by Arnaldo Carvalho de Melo

Em Sat, Mar 05, 2022 at 09:33:59PM +0100, Jiri Olsa escreveu: > On Fri, Mar 04, 2022 at 09:09:55AM +0000, James Clark wrote: > > Changes since v1: > > * Add read lock around dso find > > * Bracket style fix > > > > Hi, > > > > We are seeing an issue with doing Coresight decode off target where > > initially the correct dso from ~/.debug is used, but after a new thread > > in the perf.data file is passed with its mmap record, the local version > > of the dso is picked up instead. This happens if the binary exists in the > > same path on both devices, for example /bin/ls. > > > > Initially when parsing the build-ids in the header, the dso for /bin/ls > > will be created, and the file will correctly point to > > ~/.debug/bin/ls/2f15ad836be3339dec0e2e6a3c637e08e48aacbd/elf, but for any > > new threads or mmaps that are also for /bin/ls, they will not have a > > build-id set so they point to /bin/ls on the local machine rather than the > > debug folder. > > > > To fix this I made it possible to look up which existing dsos have > > build id's set that originate from the header and then copy that build-id > > onto the new dso if the name matches. Another way to do it would > > be to stop comparing the mmap id so it matches on filename only, but I > > think we do want to differentiate between different mmaps, even if they > > have the same name, which is how it works in this version. > > > > Applies to perf/core 56dce8681 > > > > James Clark (1): > > perf: Set build-id using build-id header on new mmap records > > Acked-by: Jiri Olsa <jolsa(a)kernel.org> Thanks, applied. - Arnaldo

2 years, 9 months

[PATCH 01/12] perf test: Shell - Limit to only run executable scripts in tests

by carsten.haitzler＠foss.arm.com

From: Carsten Haitzler <carsten.haitzler(a)arm.com> Perf test's shell runner will just run everything in the tests directory (as long as it's not another directory or does not begin with a dot), but sometimes you find files in there that are not shell scripts - perf.data output for example if you do some testing and then the next time you run perf test it tries to run these. Check the files are executable so they are actually intended to be test scripts and not just some "random junk" files there. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> --- tools/perf/tests/builtin-test.c | 4 +++- tools/perf/util/path.c | 12 ++++++++++++ tools/perf/util/path.h | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index 8cb5a1c3489e..ece272b55587 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -295,7 +295,9 @@ static const char *shell_test__description(char *description, size_t size, #define for_each_shell_test(entlist, nr, base, ent) \ for (int __i = 0; __i < nr && (ent = entlist[__i]); __i++) \ - if (!is_directory(base, ent) && ent->d_name[0] != '.') + if (!is_directory(base, ent) && \ + is_executable_file(base, ent) && \ + ent->d_name[0] != '.') static const char *shell_tests__dir(char *path, size_t size) { diff --git a/tools/perf/util/path.c b/tools/perf/util/path.c index caed0336429f..7dde8c230ae8 100644 --- a/tools/perf/util/path.c +++ b/tools/perf/util/path.c @@ -92,3 +92,15 @@ bool is_directory(const char *base_path, const struct dirent *dent) return S_ISDIR(st.st_mode); } + +bool is_executable_file(const char *base_path, const struct dirent *dent) +{ + char path[PATH_MAX]; + struct stat st; + + sprintf(path, "%s/%s", base_path, dent->d_name); + if (stat(path, &st)) + return false; + + return !S_ISDIR(st.st_mode) && (st.st_mode & S_IXUSR); +} diff --git a/tools/perf/util/path.h b/tools/perf/util/path.h index 083429b7efa3..d94902c22222 100644 --- a/tools/perf/util/path.h +++ b/tools/perf/util/path.h @@ -12,5 +12,6 @@ int path__join3(char *bf, size_t size, const char *path1, const char *path2, con bool is_regular_file(const char *file); bool is_directory(const char *base_path, const struct dirent *dent); +bool is_executable_file(const char *base_path, const struct dirent *dent); #endif /* _PERF_PATH_H */ -- 2.32.0

2 years, 9 months

OpenCSD release - version 1.3.0

by Mike Leach

Version 1.3.0 of OpenCSD is now released. This updates the decoder for changes made to trace to account for new features in Architecture versions Armv8-A v8.8 and Armv9-A v9.3 See README.md for addtional details. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

[GIT PULL] coresight changes for v5.18

by Suzuki K Poulose

Hi Greg Please find the pull request for coresight subsystem for v5.18. Suzuki The following changes since commit dfd42facf1e4ada021b939b4e19c935dcdd55566: Linux 5.17-rc3 (2022-02-06 12:20:50 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.18 for you to fetch changes up to b54f53bc11a584713f79a704c70c488489f524b8: coresight: Drop unused 'none' enum value for each component (2022-02-28 09:51:40 -0700) ---------------------------------------------------------------- coresight: changes for v5.18 The coresight update for v5.18 includes - TRBE erratum workarounds for Arm Cortex-A510 - Fixes for leaking root namespace PIDs into non-root namespace trace sessions - Miscellaneous fixes and cleanups Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Anshuman Khandual (4): coresight: trbe: Work around the ignored system register writes coresight: trbe: Work around the invalid prohibited states coresight: trbe: Work around the trace data corruption coresight: Drop unused 'none' enum value for each component James Clark (2): coresight: Fix TRCCONFIGR.QE sysfs interface coresight: no-op refactor to make INSTP0 check more idiomatic Leo Yan (4): coresight: etm4x: Add lock for reading virtual context ID comparator coresight: etm4x: Don't use virtual contextID for non-root PID namespace coresight: etm4x: Don't trace PID for non-root PID namespace coresight: etm3x: Don't trace PID for non-root PID namespace Miaoqian Lin (1): coresight: syscfg: Fix memleak on registration failure in cscfg_create_device Rafael J. Wysocki (1): hwtracing: coresight: Replace acpi_bus_get_device() Sudeep Holla (1): coresight: trbe: Move check for kernel page table isolation from EL0 to probe arch/arm64/Kconfig | 6 +- drivers/hwtracing/coresight/coresight-core.c | 3 - drivers/hwtracing/coresight/coresight-etm3x-core.c | 4 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 38 ++++++- drivers/hwtracing/coresight/coresight-platform.c | 8 +- drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 125 +++++++++++++++------ drivers/hwtracing/coresight/coresight-trbe.h | 8 -- include/linux/coresight.h | 5 - 10 files changed, 149 insertions(+), 62 deletions(-)

2 years, 9 months

Re: [GIT PULL] coresight changes for v5.18

by Mathieu Poirier

On Thu, 10 Mar 2022 at 14:44, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > On Thu, Mar 03, 2022 at 11:03:01PM +0000, Suzuki K Poulose wrote: > > Hi Greg > > > > Please find the pull request for coresight subsystem for v5.18. > > > > Suzuki > > > > The following changes since commit dfd42facf1e4ada021b939b4e19c935dcdd55566: > > > > Linux 5.17-rc3 (2022-02-06 12:20:50 -0800) > > > > are available in the Git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.18 > > > > for you to fetch changes up to b54f53bc11a584713f79a704c70c488489f524b8: > > > > coresight: Drop unused 'none' enum value for each component (2022-02-28 09:51:40 -0700) > > I have the following errors when pulling this tree and having the > scripts check the commits: > > Commit 5340bf5df9d2 ("coresight: syscfg: Fix memleak on registration failure in cscfg_create_device") > committer Signed-off-by missing > author email: linmq006(a)gmail.com > committer email: suzuki.poulose(a)arm.com > Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > Commit 91a2f2941df2 ("coresight: Fix TRCCONFIGR.QE sysfs interface") > committer Signed-off-by missing > author email: james.clark(a)arm.com > committer email: suzuki.poulose(a)arm.com > Signed-off-by: James Clark <james.clark(a)arm.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > Commit 7f4cd3375906 ("coresight: trbe: Work around the trace data corruption") > committer Signed-off-by missing > author email: anshuman.khandual(a)arm.com > committer email: suzuki.poulose(a)arm.com > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > Commit 0ecf2c747437 ("coresight: trbe: Work around the invalid prohibited states") > committer Signed-off-by missing > author email: anshuman.khandual(a)arm.com > committer email: suzuki.poulose(a)arm.com > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > Commit 8b6927d0adad ("coresight: trbe: Work around the ignored system register writes") > committer Signed-off-by missing > author email: anshuman.khandual(a)arm.com > committer email: suzuki.poulose(a)arm.com > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> > > > What went wrong??? > (Sigh) I know what happened. The tree was rebased from -rc1 to -rc3 to pick up a dependency with the aarch64 tree that was needed for a patch. In doing so the original committer information was overwritten, which is what the script is complaining about. We will send you another pull request. > linux-next didn't complain about this already? > It did not. Thanks for the patience, Mathieu

2 years, 9 months

Re: [PATCH RESEND 0/1] arm64: dts: Juno CTI device tree additions

by Mike Leach

Hi Sudeep, On Wed, 9 Mar 2022 at 11:50, Sudeep Holla <sudeep.holla(a)arm.com> wrote: > > On Wed, Mar 09, 2022 at 11:31:16AM +0000, Mike Leach wrote: > > This is a resend of a patch from some time ago (04/2020)[1] which seems to > > have fallen through the cracks - most likely as last time I mistakenly > > tagged it as dt-bindings: rather than dts: > > > > Quite likely, but I vaguely remember this and I assume the bindings had > on-going discussions at that time. > > > I am planning a release of additional CTI configuration examples, which > > include some for Juno - so this is now needed upstream to support that work. > > > > Patch unchanged, other than a correction to the subject. > > > > That may not work. I haven't tried applying but it would be good to > post it rebasing on -next at this moment or after v5.18-rc1 is released. > I have already sent v5.18 material, so I need to queue this for v5.19. > So preferable post the rebase version at v5.18-rc1 in 2+ weeks time. > We have had some restructuring including the new scmi version of DTB > in the mainline or queued in -next at the moment. > I did check it on coresight/next (5.17-rc3) and it was fine. However re-doing for 5.18 is no problem as anything that depends on it will be on there or later anyway. Will rebase and repost when 5.18-rc1 becomes available. Thanks Mike > Sorry for missing this last time. > > > [1] https://lore.kernel.org/linux-arm-kernel/20200415201330.15894-1-mike.leach@… > > > > > > Mike Leach (1): > > arm64: dts: arm: Juno - add CTI entries to device tree > > > > No need of the cover letter for one patch, just post the patch next time. > > -- > Regards, > Sudeep -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

[PATCH RESEND 0/1] arm64: dts: Juno CTI device tree additions

by Mike Leach

This is a resend of a patch from some time ago (04/2020)[1] which seems to have fallen through the cracks - most likely as last time I mistakenly tagged it as dt-bindings: rather than dts: I am planning a release of additional CTI configuration examples, which include some for Juno - so this is now needed upstream to support that work. Patch unchanged, other than a correction to the subject. [1] https://lore.kernel.org/linux-arm-kernel/20200415201330.15894-1-mike.leach@… Mike Leach (1): arm64: dts: arm: Juno - add CTI entries to device tree arch/arm64/boot/dts/arm/juno-base.dtsi | 162 +++++++++++++++++++++- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 ++++- arch/arm64/boot/dts/arm/juno-r1.dts | 25 ++++ arch/arm64/boot/dts/arm/juno-r2.dts | 25 ++++ arch/arm64/boot/dts/arm/juno.dts | 25 ++++ 5 files changed, 269 insertions(+), 5 deletions(-) -- 2.17.1

2 years, 9 months

Re: [PATCH v2] coresight: core: Fix coresight device probe failure issue

by Suzuki K Poulose

Hi Jinlong On 04/03/2022 08:23, Mao Jinlong wrote: > It is possibe that probe failure issue happens when the device > and its child_device's probe happens at the same time. > In coresight_make_links, has_conns_grp is true for parent, but > has_conns_grp is false for child device as has_conns_grp is set > to true in coresight_create_conns_sysfs_group. The probe of parent > device will fail at this condition. Add has_conns_grp check for > child device before make the links and make the process from > device_register to connection_create be atomic to avoid this > probe failure issue. > > Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Suggested-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 88653d1c06a4..b3e3bc59c09b 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -1382,7 +1382,7 @@ static int coresight_fixup_device_conns(struct coresight_device *csdev) > continue; > conn->child_dev = > coresight_find_csdev_by_fwnode(conn->child_fwnode); > - if (conn->child_dev) { > + if (conn->child_dev && conn->child_dev->has_conns_grp) { > ret = coresight_make_links(csdev, conn, > conn->child_dev); > if (ret) > @@ -1594,7 +1594,8 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL); > if (!refcnts) { > ret = -ENOMEM; > - goto err_free_csdev; > + kfree(csdev); > + goto err_out; > } > > csdev->refcnt = refcnts; > @@ -1619,8 +1620,10 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > csdev->dev.fwnode = fwnode_handle_get(dev_fwnode(desc->dev)); > dev_set_name(&csdev->dev, "%s", desc->name); > > + mutex_lock(&coresight_mutex); > ret = device_register(&csdev->dev); > if (ret) { > + mutex_unlock(&coresight_mutex); > put_device(&csdev->dev); > /* > * All resources are free'd explicitly via > @@ -1634,6 +1637,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > ret = etm_perf_add_symlink_sink(csdev); > > if (ret) { > + mutex_unlock(&coresight_mutex); > device_unregister(&csdev->dev); > /* > * As with the above, all resources are free'd > @@ -1645,8 +1649,6 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > } > } > > - mutex_lock(&coresight_mutex); > - > ret = coresight_create_conns_sysfs_group(csdev); > if (!ret) > ret = coresight_fixup_device_conns(csdev); > @@ -1663,8 +1665,6 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) > > return csdev; > > -err_free_csdev: > - kfree(csdev); > err_out: > /* Cleanup the connection information */ > coresight_release_platform_data(NULL, desc->pdata); Could we consolidate the unlock sequence to a single point with something like this (untested): diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index af00dca8d1ac..198ee140c6e6 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1571,6 +1571,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) int nr_refcnts = 1; atomic_t *refcnts = NULL; struct coresight_device *csdev; + bool registered = false; csdev = kzalloc(sizeof(*csdev), GFP_KERNEL); if (!csdev) { @@ -1591,7 +1592,8 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) refcnts = kcalloc(nr_refcnts, sizeof(*refcnts), GFP_KERNEL); if (!refcnts) { ret = -ENOMEM; - goto err_free_csdev; + kfree(csdev); + goto err_out; } csdev->refcnt = refcnts; @@ -1616,6 +1618,13 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) csdev->dev.fwnode = fwnode_handle_get(dev_fwnode(desc->dev)); dev_set_name(&csdev->dev, "%s", desc->name); + /* + * Make sure the device registration and the connection fixup + * are synchronised, so that we don't see uninitialised devices + * on the coresight bus while trying to resolve the connections. + */ + mutex_lock(&coresight_mutex); + ret = device_register(&csdev->dev); if (ret) { put_device(&csdev->dev); @@ -1623,7 +1632,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) * All resources are free'd explicitly via * coresight_device_release(), triggered from put_device(). */ - goto err_out; + goto out_unlock; } if (csdev->type == CORESIGHT_DEV_TYPE_SINK || @@ -1638,11 +1647,11 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) * from put_device(), which is in turn called from * function device_unregister(). */ - goto err_out; + goto out_unlock; } } - - mutex_lock(&coresight_mutex); + /* Device is now registered */ + registered = true; ret = coresight_create_conns_sysfs_group(csdev); if (!ret) @@ -1652,16 +1661,15 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) if (!ret && cti_assoc_ops && cti_assoc_ops->add) cti_assoc_ops->add(csdev); +out_unlock: mutex_unlock(&coresight_mutex); - if (ret) { + /* Success */ + if (!ret) + return csdev; + + /* Unregister the device if needed */ + if (registered) coresight_unregister(csdev); - return ERR_PTR(ret); - } - - return csdev; - -err_free_csdev: - kfree(csdev); err_out: /* Cleanup the connection information */ coresight_release_platform_data(NULL, desc->pdata); -- 2.35.1

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CoreSight March 2022