CoreSight November 2023

coresight@lists.linaro.org

10 participants
36 discussions

[PATCH] coresight: etm4x: Fix width of CCITMIN field

by James Clark

CCITMIN is a 12 bit field and doesn't fit in a u8, so extend it to u16. This probably wasn't an issue previously because values higher than 255 never occurred. But since commit 0f55b43dedcd ("coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus"), a comparison with 256 was done to enable the errata, generating the following W=1 build error: coresight-etm4x-core.c:1188:24: error: result of comparison of constant 256 with expression of type 'u8' (aka 'unsigned char') is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (drvdata->ccitmin == 256) Cc: stable(a)vger.kernel.org Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata") Signed-off-by: James Clark <james.clark(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 20e2e4cb7614..da17b6c49b0f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1036,7 +1036,7 @@ struct etmv4_drvdata { u8 ctxid_size; u8 vmid_size; u8 ccsize; - u8 ccitmin; + u16 ccitmin; u8 s_ex_level; u8 ns_ex_level; u8 q_support; -- 2.34.1

6 months, 1 week

Re: [PATCH] coresight: trbe: Fix an IS_ERR() vs NULL check

by Anshuman Khandual

On 11/2/23 13:22, Dan Carpenter wrote: > This code was changed from using coresight_get_platform_data() which > returns error pointers to devm_kzalloc() which returns NULL. Update > the check to match. > > Fixes: 4817af577b82 ("coresight: trbe: Add a representative coresight_platform_data for TRBE") > Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index a3954be7b1f3..228ea85cfc74 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -1265,7 +1265,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp > * into the device for that purpose. > */ > desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL); > - if (IS_ERR(desc.pdata)) > + if (!desc.pdata) Although this might not be applicable here, given the input size is always valid, devm_kzalloc() might also return ZERO_SIZE_PTR as well. /* * ZERO_SIZE_PTR will be returned for zero sized kmalloc requests. * * Dereferencing ZERO_SIZE_PTR will lead to a distinct access fault. * * ZERO_SIZE_PTR can be passed to kfree though in the same way that NULL can. * Both make kfree a no-op. */ #define ZERO_SIZE_PTR ((void *)16) #define ZERO_OR_NULL_PTR(x) ((unsigned long)(x) <= \ (unsigned long)ZERO_SIZE_PTR) Hence should ZERO_OR_NULL_PTR() check be used instead ? > goto cpu_clear; > > desc.type = CORESIGHT_DEV_TYPE_SINK;

6 months, 1 week

[PATCH v2 0/8] Add support to configure TPDM CMB subunit

by Tao Zhang

Introduction of TPDM CMB(Continuous Multi Bit) subunit CMB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The CMB makes trace elements in two modes. In �continuous� mode, every valid data cycle creates an element. In �trace on change� mode, when valid data changes on the bus, a trace element is created. In continuous mode, all cycles where this condition is true create trace elements. In trace on change mode, a data element is only when the previously sampled input is different from the current sampled input. The CMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure CMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports CMB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/684c000.tpdm/tpdm0# ls -l -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 cmb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 cmb_ts_all drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Ja? 1 00:00 power --w------- 1 root root 4096 Jan 1 00:00 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support CMB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset_dataset echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_mode echo 1 > /sys/bus/coresight/devices/tpdm0/cmb_patt/enable_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_patt/tpmr0 echo 0 > /sys/bus/coresight/devices/tpdm0/cmb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/cmb_trig_patt/xpr1 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source This patch series depends on patch "[v1] coresight-tpdm: Correct the property name of MSR number" https://patchwork.kernel.org/project/linux-arm-kernel/patch/1698128353-3115… codelinaro link: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-cmb-v2 Changes in V2: 1. Optimizate and modify this patch series based on the patch series "Add support to configure TPDM CMB subunit". 2. Modify the functions that read the element size of DSB/CMB in TPDA driver. Tao Zhang (8): dt-bindings: arm: Add support for CMB element size coresight-tpda: Add support to configure CMB element coresight-tpdm: Add CMB dataset support coresight-tpdm: Add support to configure CMB coresight-tpdm: Add pattern registers support for CMB coresight-tpdm: Add timestamp control register support for the CMB dt-bindings: arm: Add support for TPDM CMB MSR register coresight-tpdm: Add msr register support for CMB .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 83 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 37 ++ drivers/hwtracing/coresight/coresight-tpda.c | 108 +++--- drivers/hwtracing/coresight/coresight-tpda.h | 6 + drivers/hwtracing/coresight/coresight-tpdm.c | 390 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 87 +++++ 6 files changed, 663 insertions(+), 48 deletions(-) -- 2.7.4

6 months, 1 week

[PATCH v1] coresight-tpdm: Correct the property name of MSR number

by Tao Zhang

Correct the property name of the DSB MSR number that needs to be read in TPDM driver. The right property name is "qcom,dsb-msrs-num". Fixes： 90a7371cb08d ("coresight-tpdm: Add nodes for dsb msr support") Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tpdm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index b25284e..97654aa 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -892,7 +892,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) if (drvdata && tpdm_has_dsb_dataset(drvdata)) of_property_read_u32(drvdata->dev->of_node, - "qcom,dsb_msr_num", &drvdata->dsb_msr_num); + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); /* Set up coresight component description */ desc.name = coresight_alloc_device_name(&tpdm_devs, dev); -- 2.7.4

6 months, 1 week

[PATCH v2] coresight: etm4x: Fix width of CCITMIN field

by James Clark

CCITMIN is a 12 bit field and doesn't fit in a u8, so extend it to u16. This probably wasn't an issue previously because values higher than 255 never occurred. But since commit 0f55b43dedcd ("coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus"), a comparison with 256 was done to enable the errata, generating the following W=1 build error: coresight-etm4x-core.c:1188:24: error: result of comparison of constant 256 with expression of type 'u8' (aka 'unsigned char') is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (drvdata->ccitmin == 256) Cc: stable(a)vger.kernel.org Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Reviewed-by: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: James Clark <james.clark(a)arm.com> --- Changes since V1: * Change the fixes commit to the original addition of ccitmin, rather than the last refactor of the struct. drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 20e2e4cb7614..da17b6c49b0f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1036,7 +1036,7 @@ struct etmv4_drvdata { u8 ctxid_size; u8 vmid_size; u8 ccsize; - u8 ccitmin; + u16 ccitmin; u8 s_ex_level; u8 ns_ex_level; u8 q_support; -- 2.34.1

6 months, 1 week

Re: [PATCH v2 7/8] dt-bindings: arm: Add support for TPDM CMB MSR register

by Tao Zhang

On 10/27/2023 5:27 AM, Rob Herring wrote: > On Wed, Oct 25, 2023 at 10:53:27AM +0800, Tao Zhang wrote: >> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) >> for TPDM. It specifies the number of CMB MSR registers supported by >> the TDPM. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> index f9a2025..a586b80a 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml >> @@ -69,6 +69,15 @@ properties: >> minimum: 0 >> maximum: 32 >> >> + qcom,cmb-msrs-num: >> + description: >> + Specifies the number of CMB MSR(mux select register) registers supported >> + by the monitor. If this property is not configured or set to 0, it means >> + this TPDM doesn't support CMB MSR. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 0 >> + maximum: 32 > default: 0 If the TPDM doesn't support CMB MSR, we will not configure this property. Set to 0 to indicate that CMB MSR is not supported and is only an optional method. Is it necessary to add this "default" value here? Best, Tao >> + >> clocks: >> maxItems: 1 >> >> @@ -124,6 +133,7 @@ examples: >> reg-names = "tpdm-base"; >> >> qcom,cmb-element-size = /bits/ 8 <64>; >> + qcom,cmb-msrs-num = <32>; >> >> clocks = <&aoss_qmp>; >> clock-names = "apb_pclk"; >> -- >> 2.7.4 >>

6 months, 1 week

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CoreSight November 2023