CoreSight December 2023

coresight@lists.linaro.org

10 participants
30 discussions

Re: [PATCH v1 1/2] dt-bindings: arm: coresight: Update the pattern of ete node name

by Jinlong Mao

On 12/20/2023 11:50 PM, Krzysztof Kozlowski wrote: > On 20/12/2023 15:05, Mao Jinlong wrote: >> Update the suffix for ete node name to be with "-". >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> .../bindings/arm/arm,embedded-trace-extension.yaml | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml >> index f725e6940993..cbf583d34029 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml >> @@ -23,7 +23,7 @@ description: | >> >> properties: >> $nodename: >> - pattern: "^ete([0-9a-f]+)$" >> + pattern: "^ete-([0-9a-f]+)$" > > My concerns are not resolved. Why is it here in the first place? Hi Krzysztof, ETE is acronym of embedded trace extension. The number of the name is the same as the number of the CPU it belongs to. Hi Suzuki, Please help to comment on this. Thanks Jinlong Mao > > Best regards, > Krzysztof >

4 months, 2 weeks

Re: [PATCH RFC V2 1/4] perf/core: Add aux_pause, aux_resume, aux_start_paused

by Suzuki K Poulose

On 08/12/2023 17:24, Adrian Hunter wrote: > Hardware traces, such as instruction traces, can produce a vast amount of > trace data, so being able to reduce tracing to more specific circumstances > can be useful. > > The ability to pause or resume tracing when another event happens, can do > that. > > Add ability for an event to "pause" or "resume" AUX area tracing. > > Add aux_pause bit to perf_event_attr to indicate that, if the event > happens, the associated AUX area tracing should be paused. Ditto > aux_resume. Do not allow aux_pause and aux_resume to be set together. > > Add aux_start_paused bit to perf_event_attr to indicate to an AUX area > event that it should start in a "paused" state. > > Add aux_paused to struct perf_event for AUX area events to keep track of > the "paused" state. aux_paused is initialized to aux_start_paused. > > Add PERF_EF_PAUSE and PERF_EF_RESUME modes for ->stop() and ->start() > callbacks. Call as needed, during __perf_event_output(). Add > aux_in_pause_resume to struct perf_buffer to prevent races with the NMI > handler. Pause/resume in NMI context will miss out if it coincides with > another pause/resume. > > To use aux_pause or aux_resume, an event must be in a group with the AUX > area event as the group leader. > > Example (requires Intel PT and tools patches also): > > $ perf record --kcore -e '{intel_pt/aux-start-paused/k,syscalls:sys_enter_newuname/aux-resume/,syscalls:sys_exit_newuname/aux-pause/}' uname > Linux > [ perf record: Woken up 1 times to write data ] > [ perf record: Captured and wrote 0.041 MB perf.data ] > $ perf script --call-trace > uname 5712 [007] 83.855580930: name: 0x7ffd9dcebec0 > uname 5712 [007] 83.855582518: psb offs: 0 > uname 5712 [007] 83.855582518: cbr: 42 freq: 4205 MHz (150%) > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) __x64_sys_newuname > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) down_read > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) __cond_resched > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_add > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) in_lock_functions > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_sub > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) up_read > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_add > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) in_lock_functions > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) preempt_count_sub > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) _copy_to_user > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) syscall_exit_to_user_mode > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) syscall_exit_work > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_syscall_exit > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_trace_buf_alloc > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_swevent_get_recursion_context > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_tp_event > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_trace_buf_update > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) tracing_gen_ctx_irq_test > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_swevent_event > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __perf_event_account_interrupt > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __this_cpu_preempt_check > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) perf_event_output_forward > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) perf_event_aux_pause > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) ring_buffer_get > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __rcu_read_lock > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __rcu_read_unlock > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) pt_event_stop > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583973: ([kernel.kallsyms]) native_write_msr > uname 5712 [007] 83.855583973: ([kernel.kallsyms]) native_write_msr > uname 5712 [007] 83.855584175: 0x0 > > Signed-off-by: Adrian Hunter <adrian.hunter(a)intel.com> > --- > include/linux/perf_event.h | 15 +++++++ > include/uapi/linux/perf_event.h | 11 ++++- > kernel/events/core.c | 72 +++++++++++++++++++++++++++++++-- > kernel/events/internal.h | 1 + > 4 files changed, 95 insertions(+), 4 deletions(-) > > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h > index e85cd1c0eaf3..252c4aac3b79 100644 > --- a/include/linux/perf_event.h > +++ b/include/linux/perf_event.h > @@ -291,6 +291,7 @@ struct perf_event_pmu_context; > #define PERF_PMU_CAP_NO_EXCLUDE 0x0040 > #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 > #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 > +#define PERF_PMU_CAP_AUX_PAUSE 0x0200 > > struct perf_output_handle; > > @@ -363,6 +364,8 @@ struct pmu { > #define PERF_EF_START 0x01 /* start the counter when adding */ > #define PERF_EF_RELOAD 0x02 /* reload the counter when starting */ > #define PERF_EF_UPDATE 0x04 /* update the counter when stopping */ > +#define PERF_EF_PAUSE 0x08 /* AUX area event, pause tracing */ > +#define PERF_EF_RESUME 0x10 /* AUX area event, resume tracing */ > > /* > * Adds/Removes a counter to/from the PMU, can be done inside a > @@ -402,6 +405,15 @@ struct pmu { > * > * ->start() with PERF_EF_RELOAD will reprogram the counter > * value, must be preceded by a ->stop() with PERF_EF_UPDATE. > + * > + * ->stop() with PERF_EF_PAUSE will stop as simply as possible. Will not > + * overlap another ->stop() with PERF_EF_PAUSE nor ->start() with > + * PERF_EF_RESUME. > + * > + * ->start() with PERF_EF_RESUME will start as simply as possible but > + * only if the counter is not otherwise stopped. Will not overlap > + * another ->start() with PERF_EF_RESUME nor ->stop() with > + * PERF_EF_PAUSE. > */ > void (*start) (struct perf_event *event, int flags); > void (*stop) (struct perf_event *event, int flags); > @@ -797,6 +809,9 @@ struct perf_event { > /* for aux_output events */ > struct perf_event *aux_event; > > + /* for AUX area events */ > + unsigned int aux_paused; > + > void (*destroy)(struct perf_event *); > struct rcu_head rcu_head; > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index 39c6a250dd1b..437bc2a8d50c 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -507,7 +507,16 @@ struct perf_event_attr { > __u16 sample_max_stack; > __u16 __reserved_2; > __u32 aux_sample_size; > - __u32 __reserved_3; > + > + union { > + __u32 aux_output_cfg; > + struct { > + __u64 aux_pause : 1, /* on overflow, pause AUX area tracing */ Did you mean __u32 ? Otherwise look good to me. Suzuki > + aux_resume : 1, /* on overflow, resume AUX area tracing */ > + aux_start_paused : 1, /* start AUX area tracing paused */ > + __reserved_3 : 29; > + }; > + }; > > /* > * User provided data if sigtrap=1, passed back to user via > diff --git a/kernel/events/core.c b/kernel/events/core.c > index 4c72a41f11af..c1e11884d06e 100644 > --- a/kernel/events/core.c > +++ b/kernel/events/core.c > @@ -2060,7 +2060,8 @@ static void perf_put_aux_event(struct perf_event *event) > > static bool perf_need_aux_event(struct perf_event *event) > { > - return !!event->attr.aux_output || !!event->attr.aux_sample_size; > + return event->attr.aux_output || event->attr.aux_sample_size || > + event->attr.aux_pause || event->attr.aux_resume; > } > > static int perf_get_aux_event(struct perf_event *event, > @@ -2085,6 +2086,10 @@ static int perf_get_aux_event(struct perf_event *event, > !perf_aux_output_match(event, group_leader)) > return 0; > > + if ((event->attr.aux_pause || event->attr.aux_resume) && > + !(group_leader->pmu->capabilities & PERF_PMU_CAP_AUX_PAUSE)) > + return 0; > + > if (event->attr.aux_sample_size && !group_leader->pmu->snapshot_aux) > return 0; > > @@ -7773,6 +7778,47 @@ void perf_prepare_header(struct perf_event_header *header, > WARN_ON_ONCE(header->size & 7); > } > > +static void __perf_event_aux_pause(struct perf_event *event, bool pause) > +{ > + if (pause) { > + if (!READ_ONCE(event->aux_paused)) { > + WRITE_ONCE(event->aux_paused, 1); > + event->pmu->stop(event, PERF_EF_PAUSE); > + } > + } else { > + if (READ_ONCE(event->aux_paused)) { > + WRITE_ONCE(event->aux_paused, 0); > + event->pmu->start(event, PERF_EF_RESUME); > + } > + } > +} > + > +static void perf_event_aux_pause(struct perf_event *event, bool pause) > +{ > + struct perf_buffer *rb; > + unsigned long flags; > + > + if (WARN_ON_ONCE(!event)) > + return; > + > + rb = ring_buffer_get(event); > + if (!rb) > + return; > + > + local_irq_save(flags); > + /* Guard against NMI, NMI loses here */ > + if (READ_ONCE(rb->aux_in_pause_resume)) > + goto out_restore; > + WRITE_ONCE(rb->aux_in_pause_resume, 1); > + barrier(); > + __perf_event_aux_pause(event, pause); > + barrier(); > + WRITE_ONCE(rb->aux_in_pause_resume, 0); > +out_restore: > + local_irq_restore(flags); > + ring_buffer_put(rb); > +} > + > static __always_inline int > __perf_event_output(struct perf_event *event, > struct perf_sample_data *data, > @@ -7786,6 +7832,9 @@ __perf_event_output(struct perf_event *event, > struct perf_event_header header; > int err; > > + if (event->attr.aux_pause) > + perf_event_aux_pause(event->aux_event, true); > + > /* protect the callchain buffers */ > rcu_read_lock(); > > @@ -7802,6 +7851,10 @@ __perf_event_output(struct perf_event *event, > > exit: > rcu_read_unlock(); > + > + if (event->attr.aux_resume) > + perf_event_aux_pause(event->aux_event, false); > + > return err; > } > > @@ -11941,10 +11994,23 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, > } > > if (event->attr.aux_output && > - !(pmu->capabilities & PERF_PMU_CAP_AUX_OUTPUT)) { > + (!(pmu->capabilities & PERF_PMU_CAP_AUX_OUTPUT) || > + event->attr.aux_pause || event->attr.aux_resume)) { > + err = -EOPNOTSUPP; > + goto err_pmu; > + } > + > + if (event->attr.aux_pause && event->attr.aux_resume) { > + err = -EINVAL; > + goto err_pmu; > + } > + > + if (event->attr.aux_start_paused && > + !(pmu->capabilities & PERF_PMU_CAP_AUX_PAUSE)) { > err = -EOPNOTSUPP; > goto err_pmu; > } > + event->aux_paused = event->attr.aux_start_paused; > > if (cgroup_fd != -1) { > err = perf_cgroup_connect(cgroup_fd, event, attr, group_leader); > @@ -12741,7 +12807,7 @@ perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu, > * Grouping is not supported for kernel events, neither is 'AUX', > * make sure the caller's intentions are adjusted. > */ > - if (attr->aux_output) > + if (attr->aux_output || attr->aux_output_cfg) > return ERR_PTR(-EINVAL); > > event = perf_event_alloc(attr, cpu, task, NULL, NULL, > diff --git a/kernel/events/internal.h b/kernel/events/internal.h > index 5150d5f84c03..3320f78117dc 100644 > --- a/kernel/events/internal.h > +++ b/kernel/events/internal.h > @@ -51,6 +51,7 @@ struct perf_buffer { > void (*free_aux)(void *); > refcount_t aux_refcount; > int aux_in_sampling; > + int aux_in_pause_resume; > void **aux_pages; > void *aux_priv; >

4 months, 2 weeks

Re: [PATCH RFC V3 4/4] coresight: Have a stab at support for pause / resume

by James Clark

On 15/12/2023 06:42, Adrian Hunter wrote: > For discussion only, un-tested... > If anyone wants to test Coresight, the diff below is required to get the most basic use case working. It also probably needs more thought and some edge case handling: diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 596c01e37624..bd0767356277 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -556,7 +556,8 @@ static void etm_event_stop(struct perf_event *event, int mode) struct etm_event_data *event_data; struct list_head *path; - if (mode & PERF_EF_PAUSE && !READ_ONCE(ctxt->pr_allowed)) + if ((mode & PERF_EF_PAUSE && !READ_ONCE(ctxt->pr_allowed)) || + event->hw.state == PERF_HES_STOPPED) return; WRITE_ONCE(ctxt->pr_allowed, 0); @@ -573,9 +574,6 @@ static void etm_event_stop(struct perf_event *event, int mode) /* Clear the event_data as this ETM is stopping the trace. */ ctxt->event_data = NULL; - if (event->hw.state == PERF_HES_STOPPED) - goto out_pr_allowed; - /* We must have a valid event_data for a running event */ if (WARN_ON(!event_data)) return; @@ -586,7 +584,7 @@ static void etm_event_stop(struct perf_event *event, int mode) * nothing needs to be torn down other than outputting a * zero sized record. */ - if (handle->event && (mode & PERF_EF_UPDATE) && + if (handle->event && (mode & (PERF_EF_UPDATE | PERF_EF_PAUSE)) && !cpumask_test_cpu(cpu, &event_data->mask)) { event->hw.state = PERF_HES_STOPPED; perf_aux_output_end(handle, 0); @@ -616,7 +614,7 @@ static void etm_event_stop(struct perf_event *event, int mode) * handle due to lack of buffer space), we don't * have to do anything here. */ - if (handle->event && (mode & PERF_EF_UPDATE)) { + if (handle->event && (mode & (PERF_EF_UPDATE | PERF_EF_PAUSE))) { if (WARN_ON_ONCE(handle->event != event)) return; @@ -646,7 +644,6 @@ static void etm_event_stop(struct perf_event *event, int mode) /* Disabling the path make its elements available to other sessions */ coresight_disable_path(path); -out_pr_allowed: if (mode & PERF_EF_PAUSE) WRITE_ONCE(ctxt->pr_allowed, 1); } @@ -656,7 +653,7 @@ static int etm_event_add(struct perf_event *event, int mode) int ret = 0; struct hw_perf_event *hwc = &event->hw; - if (mode & PERF_EF_START && !READ_ONCE(event->aux_paused)) { + if (mode & PERF_EF_START) { etm_event_start(event, 0); if (hwc->state & PERF_HES_STOPPED) ret = -EINVAL; -- 2.34.1

4 months, 2 weeks

Re: [PATCH RFC V2 1/4] perf/core: Add aux_pause, aux_resume, aux_start_paused

by James Clark

4 months, 2 weeks

Re: [PATCH] arm64: dts: qcom: Add coresight nodes for sm8450

by Jinlong Mao

On 12/20/2023 9:21 PM, Krzysztof Kozlowski wrote: > On 20/12/2023 14:07, Jinlong Mao wrote: >> >> >> On 12/20/2023 8:46 PM, Krzysztof Kozlowski wrote: >>> On 20/12/2023 13:40, Mao Jinlong wrote: >>>> Add coresight components on Qualcomm SM8450 Soc. The components include >>>> TMC ETF/ETR, ETE, STM, TPDM, CTI. >>>> >>>> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 742 +++++++++++++++++++++++++++ >>>> 1 file changed, 742 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> index 1783fa78bdbc..112b5a069c94 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >>>> @@ -285,6 +285,192 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { >>>> }; >>>> }; >>>> >>>> + ete0 { >>> >>> ete-0 >> Thanks for the review. >> >> In arm,embedded-trace-extension.yaml, the node name pattern is >> "^ete([0-9a-f]+)$". > > I don't understand why this binding requires ete name. It's not like it > is a generic name worth preserving. Also, the recommended suffix for > names is with '-'. > The number in the ete name should be the same as the number of the CPU. So we can know which CPU this ete belongs to from the name. I will update the binding in arm,embedded-trace-extension.yaml. Thanks Jinlong Mao > > Best regards, > Krzysztof >

4 months, 2 weeks

Re: [PATCH] arm64: dts: qcom: Add coresight nodes for sm8450

by Jinlong Mao

On 12/20/2023 8:46 PM, Krzysztof Kozlowski wrote: > On 20/12/2023 13:40, Mao Jinlong wrote: >> Add coresight components on Qualcomm SM8450 Soc. The components include >> TMC ETF/ETR, ETE, STM, TPDM, CTI. >> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 742 +++++++++++++++++++++++++++ >> 1 file changed, 742 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 1783fa78bdbc..112b5a069c94 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -285,6 +285,192 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { >> }; >> }; >> >> + ete0 { > > ete-0 Thanks for the review. In arm,embedded-trace-extension.yaml, the node name pattern is "^ete([0-9a-f]+)$". examples: # An ETE node without legacy CoreSight connections - | ete0 { compatible = "arm,embedded-trace-extension"; cpu = <&cpu_0>; }; # An ETE node with legacy CoreSight connections - | ete1 { compatible = "arm,embedded-trace-extension"; cpu = <&cpu_1>; out-ports { /* legacy coresight connection */ port { ete1_out_port: endpoint { remote-endpoint = <&funnel_in_port0>; }; }; }; }; > >> + compatible = "arm,embedded-trace-extension"; >> + cpu = <&CPU0>; >> + >> + out-ports { >> + port { >> + ete0_out_funnel_ete: endpoint { >> + remote-endpoint = <&funnel_ete_in_ete0>; > > Missing indentation. > > ... > >> + funnel_ete { > > funnel > Anyway underscores are not allowed > >> + compatible = "arm,coresight-static-funnel"; >> + >> + out-ports { >> + port { >> + funnel_ete_out_funnel_apss: endpoint { >> + remote-endpoint = >> + <&funnel_apss_in_funnel_ete>; > > Messed indentation > > Errors above look all over this patch, so fix all instances in this patch. > > Best regards, > Krzysztof >

4 months, 2 weeks

Re: [PATCH RFC V2 1/4] perf/core: Add aux_pause, aux_resume, aux_start_paused

by Arnaldo Carvalho de Melo

Em Fri, Dec 08, 2023 at 07:24:46PM +0200, Adrian Hunter escreveu: > Hardware traces, such as instruction traces, can produce a vast amount of > trace data, so being able to reduce tracing to more specific circumstances > can be useful. > The ability to pause or resume tracing when another event happens, can do > that. > Add ability for an event to "pause" or "resume" AUX area tracing. We need this as well for the usual ring buffer, 'perf report' has: --switch-off <event> Stop considering events after the occurrence of this event --switch-on <event> Consider events after the occurrence of this event And 'perf record' has: --switch-output-event Events that will cause the switch of the perf.data file, auto-selecting --switch-output=signal, the results are similar as internally the side band thread will also send a SIGUSR2 to the main one. But those are all in userspace, what you're doing is in the kernel, and for the example you used synchronous, i.e. you're only interested in what happens after you enter the syscall and then stop when the syscall exits (but here you'll catch more stuff in the AUX trace, i.e. a "race" from intel_pt inserting events in the AUX trace and then the syscall exit switching it off). Also being able to group the { resume, what-to-enable, pause } is powerful, as we could have multiple such groups to record those "slices", not just the --switch-off/--switch-on global ones. > Add aux_pause bit to perf_event_attr to indicate that, if the event > happens, the associated AUX area tracing should be paused. Ditto > aux_resume. Do not allow aux_pause and aux_resume to be set together. > > Add aux_start_paused bit to perf_event_attr to indicate to an AUX area > event that it should start in a "paused" state. > > Add aux_paused to struct perf_event for AUX area events to keep track of > the "paused" state. aux_paused is initialized to aux_start_paused. > > Add PERF_EF_PAUSE and PERF_EF_RESUME modes for ->stop() and ->start() > callbacks. Call as needed, during __perf_event_output(). Add > aux_in_pause_resume to struct perf_buffer to prevent races with the NMI > handler. Pause/resume in NMI context will miss out if it coincides with > another pause/resume. > > To use aux_pause or aux_resume, an event must be in a group with the AUX > area event as the group leader. > > Example (requires Intel PT and tools patches also): > > $ perf record --kcore -e '{intel_pt/aux-start-paused/k,syscalls:sys_enter_newuname/aux-resume/,syscalls:sys_exit_newuname/aux-pause/}' uname User interface looks nice, asks for intel_pt to be armed but start paused, collect just inside the kernel, then sets up another event to enable the collection of whatever is using the aux area, intel_pt in this case, and then one other event, sys_exit_newuname to pause it again. So this implicitely selects the CPU where the aux-resume took place and in this specific case we ended up being lucky and that process wasn't migrated to another CPU in the middle of the syscall... Scratch that, you're not tracing system wide, but just the 'uname' process being started from perf, perfect. - Arnaldo > Linux > [ perf record: Woken up 1 times to write data ] > [ perf record: Captured and wrote 0.041 MB perf.data ] > $ perf script --call-trace > uname 5712 [007] 83.855580930: name: 0x7ffd9dcebec0 > uname 5712 [007] 83.855582518: psb offs: 0 > uname 5712 [007] 83.855582518: cbr: 42 freq: 4205 MHz (150%) > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) __x64_sys_newuname > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) down_read > uname 5712 [007] 83.855582723: ([kernel.kallsyms]) __cond_resched > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_add > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) in_lock_functions > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_sub > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) up_read > uname 5712 [007] 83.855582932: ([kernel.kallsyms]) preempt_count_add > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) in_lock_functions > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) preempt_count_sub > uname 5712 [007] 83.855583348: ([kernel.kallsyms]) _copy_to_user > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) syscall_exit_to_user_mode > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) syscall_exit_work > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_syscall_exit > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_trace_buf_alloc > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_swevent_get_recursion_context > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_tp_event > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_trace_buf_update > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) tracing_gen_ctx_irq_test > uname 5712 [007] 83.855583557: ([kernel.kallsyms]) perf_swevent_event > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __perf_event_account_interrupt > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __this_cpu_preempt_check > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) perf_event_output_forward > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) perf_event_aux_pause > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) ring_buffer_get > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __rcu_read_lock > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) __rcu_read_unlock > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) pt_event_stop > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583765: ([kernel.kallsyms]) debug_smp_processor_id > uname 5712 [007] 83.855583973: ([kernel.kallsyms]) native_write_msr > uname 5712 [007] 83.855583973: ([kernel.kallsyms]) native_write_msr > uname 5712 [007] 83.855584175: 0x0 > > Signed-off-by: Adrian Hunter <adrian.hunter(a)intel.com> > --- > include/linux/perf_event.h | 15 +++++++ > include/uapi/linux/perf_event.h | 11 ++++- > kernel/events/core.c | 72 +++++++++++++++++++++++++++++++-- > kernel/events/internal.h | 1 + > 4 files changed, 95 insertions(+), 4 deletions(-) > > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h > index e85cd1c0eaf3..252c4aac3b79 100644 > --- a/include/linux/perf_event.h > +++ b/include/linux/perf_event.h > @@ -291,6 +291,7 @@ struct perf_event_pmu_context; > #define PERF_PMU_CAP_NO_EXCLUDE 0x0040 > #define PERF_PMU_CAP_AUX_OUTPUT 0x0080 > #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 > +#define PERF_PMU_CAP_AUX_PAUSE 0x0200 > > struct perf_output_handle; > > @@ -363,6 +364,8 @@ struct pmu { > #define PERF_EF_START 0x01 /* start the counter when adding */ > #define PERF_EF_RELOAD 0x02 /* reload the counter when starting */ > #define PERF_EF_UPDATE 0x04 /* update the counter when stopping */ > +#define PERF_EF_PAUSE 0x08 /* AUX area event, pause tracing */ > +#define PERF_EF_RESUME 0x10 /* AUX area event, resume tracing */ > > /* > * Adds/Removes a counter to/from the PMU, can be done inside a > @@ -402,6 +405,15 @@ struct pmu { > * > * ->start() with PERF_EF_RELOAD will reprogram the counter > * value, must be preceded by a ->stop() with PERF_EF_UPDATE. > + * > + * ->stop() with PERF_EF_PAUSE will stop as simply as possible. Will not > + * overlap another ->stop() with PERF_EF_PAUSE nor ->start() with > + * PERF_EF_RESUME. > + * > + * ->start() with PERF_EF_RESUME will start as simply as possible but > + * only if the counter is not otherwise stopped. Will not overlap > + * another ->start() with PERF_EF_RESUME nor ->stop() with > + * PERF_EF_PAUSE. > */ > void (*start) (struct perf_event *event, int flags); > void (*stop) (struct perf_event *event, int flags); > @@ -797,6 +809,9 @@ struct perf_event { > /* for aux_output events */ > struct perf_event *aux_event; > > + /* for AUX area events */ > + unsigned int aux_paused; > + > void (*destroy)(struct perf_event *); > struct rcu_head rcu_head; > > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index 39c6a250dd1b..437bc2a8d50c 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -507,7 +507,16 @@ struct perf_event_attr { > __u16 sample_max_stack; > __u16 __reserved_2; > __u32 aux_sample_size; > - __u32 __reserved_3; > + > + union { > + __u32 aux_output_cfg; > + struct { > + __u64 aux_pause : 1, /* on overflow, pause AUX area tracing */ > + aux_resume : 1, /* on overflow, resume AUX area tracing */ > + aux_start_paused : 1, /* start AUX area tracing paused */ > + __reserved_3 : 29; > + }; > + }; > > /* > * User provided data if sigtrap=1, passed back to user via > diff --git a/kernel/events/core.c b/kernel/events/core.c > index 4c72a41f11af..c1e11884d06e 100644 > --- a/kernel/events/core.c > +++ b/kernel/events/core.c > @@ -2060,7 +2060,8 @@ static void perf_put_aux_event(struct perf_event *event) > > static bool perf_need_aux_event(struct perf_event *event) > { > - return !!event->attr.aux_output || !!event->attr.aux_sample_size; > + return event->attr.aux_output || event->attr.aux_sample_size || > + event->attr.aux_pause || event->attr.aux_resume; > } > > static int perf_get_aux_event(struct perf_event *event, > @@ -2085,6 +2086,10 @@ static int perf_get_aux_event(struct perf_event *event, > !perf_aux_output_match(event, group_leader)) > return 0; > > + if ((event->attr.aux_pause || event->attr.aux_resume) && > + !(group_leader->pmu->capabilities & PERF_PMU_CAP_AUX_PAUSE)) > + return 0; > + > if (event->attr.aux_sample_size && !group_leader->pmu->snapshot_aux) > return 0; > > @@ -7773,6 +7778,47 @@ void perf_prepare_header(struct perf_event_header *header, > WARN_ON_ONCE(header->size & 7); > } > > +static void __perf_event_aux_pause(struct perf_event *event, bool pause) > +{ > + if (pause) { > + if (!READ_ONCE(event->aux_paused)) { > + WRITE_ONCE(event->aux_paused, 1); > + event->pmu->stop(event, PERF_EF_PAUSE); > + } > + } else { > + if (READ_ONCE(event->aux_paused)) { > + WRITE_ONCE(event->aux_paused, 0); > + event->pmu->start(event, PERF_EF_RESUME); > + } > + } > +} > + > +static void perf_event_aux_pause(struct perf_event *event, bool pause) > +{ > + struct perf_buffer *rb; > + unsigned long flags; > + > + if (WARN_ON_ONCE(!event)) > + return; > + > + rb = ring_buffer_get(event); > + if (!rb) > + return; > + > + local_irq_save(flags); > + /* Guard against NMI, NMI loses here */ > + if (READ_ONCE(rb->aux_in_pause_resume)) > + goto out_restore; > + WRITE_ONCE(rb->aux_in_pause_resume, 1); > + barrier(); > + __perf_event_aux_pause(event, pause); > + barrier(); > + WRITE_ONCE(rb->aux_in_pause_resume, 0); > +out_restore: > + local_irq_restore(flags); > + ring_buffer_put(rb); > +} > + > static __always_inline int > __perf_event_output(struct perf_event *event, > struct perf_sample_data *data, > @@ -7786,6 +7832,9 @@ __perf_event_output(struct perf_event *event, > struct perf_event_header header; > int err; > > + if (event->attr.aux_pause) > + perf_event_aux_pause(event->aux_event, true); > + > /* protect the callchain buffers */ > rcu_read_lock(); > > @@ -7802,6 +7851,10 @@ __perf_event_output(struct perf_event *event, > > exit: > rcu_read_unlock(); > + > + if (event->attr.aux_resume) > + perf_event_aux_pause(event->aux_event, false); > + > return err; > } > > @@ -11941,10 +11994,23 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, > } > > if (event->attr.aux_output && > - !(pmu->capabilities & PERF_PMU_CAP_AUX_OUTPUT)) { > + (!(pmu->capabilities & PERF_PMU_CAP_AUX_OUTPUT) || > + event->attr.aux_pause || event->attr.aux_resume)) { > + err = -EOPNOTSUPP; > + goto err_pmu; > + } > + > + if (event->attr.aux_pause && event->attr.aux_resume) { > + err = -EINVAL; > + goto err_pmu; > + } > + > + if (event->attr.aux_start_paused && > + !(pmu->capabilities & PERF_PMU_CAP_AUX_PAUSE)) { > err = -EOPNOTSUPP; > goto err_pmu; > } > + event->aux_paused = event->attr.aux_start_paused; > > if (cgroup_fd != -1) { > err = perf_cgroup_connect(cgroup_fd, event, attr, group_leader); > @@ -12741,7 +12807,7 @@ perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu, > * Grouping is not supported for kernel events, neither is 'AUX', > * make sure the caller's intentions are adjusted. > */ > - if (attr->aux_output) > + if (attr->aux_output || attr->aux_output_cfg) > return ERR_PTR(-EINVAL); > > event = perf_event_alloc(attr, cpu, task, NULL, NULL, > diff --git a/kernel/events/internal.h b/kernel/events/internal.h > index 5150d5f84c03..3320f78117dc 100644 > --- a/kernel/events/internal.h > +++ b/kernel/events/internal.h > @@ -51,6 +51,7 @@ struct perf_buffer { > void (*free_aux)(void *); > refcount_t aux_refcount; > int aux_in_sampling; > + int aux_in_pause_resume; > void **aux_pages; > void *aux_priv; > > -- > 2.34.1 > -- - Arnaldo

4 months, 3 weeks

Re: [PATCH v3 7/8] dt-bindings: arm: Add support for TPDM CMB MSR register

by Suzuki K Poulose

Tao Zhang, On 21/11/2023 07:24, Krzysztof Kozlowski wrote: > On 21/11/2023 03:24, Tao Zhang wrote: >> Add property "qcom,cmb_msr_num" to support CMB MSR(mux select register) >> for TPDM. It specifies the number of CMB MSR registers supported by >> the TDPM. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> >> --- > > I prefer not to take any new Qualcomm Coresight bindings or Qualcomm SoC > DTS nodes with Coresight till we fix all existing warnings. I don't know > how to fix them, so I need help with them. No such fixing happened so > far from Qcom, so pushback is my only way to get any attention. > > I already commented on this in other email thread. Are you addressing this ? Suzuki > > Best regards, > Krzysztof >

4 months, 3 weeks

Re: [PATCH v3 1/8] dt-bindings: arm: Add support for CMB element size

by Tao Zhang

On 11/21/2023 3:24 PM, Krzysztof Kozlowski wrote: > On 21/11/2023 03:24, Tao Zhang wrote: >> Add property "qcom,cmb-elem-size" to support CMB(Continuous >> Multi-Bit) element for TPDM. The associated aggregator will read >> this size before it is enabled. CMB element size currently only >> supports 32-bit and 64-bit. > >> qcom,dsb-msrs-num: >> description: >> Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) >> @@ -110,4 +119,23 @@ examples: >> }; >> }; >> >> + tpdm@6c29000 { >> + compatible = "qcom,coresight-tpdm", "arm,primecell"; >> + reg = <0x06c29000 0x1000>; >> + reg-names = "tpdm-base"; >> + >> + qcom,cmb-element-size = /bits/ 8 <64>; > One new property usually does not justify new example. Why it cannot be > added to existing example? Because the existing example tpdm "tpdm@684c000" which only supports dsb sub-unit. Most TPDMs only support one type of sub-unit. > > Anyway, I prefer not to take any new Qualcomm Coresight bindings or > Qualcomm SoC DTS nodes with Coresight till we fix all existing warnings. > I don't know how to fix them, so I need help with them. No such fixing > happened so far from Qcom, so pushback is my only way to get any attention. > > I already commented on this in other email thread. Jinlong has fixed the warnings from coresight bindings. I will prepare my next patch series soon. Best, Tao > > Best regards, > Krzysztof >

4 months, 3 weeks

[GIT PULL] coresight: Updates for linux v6.8

by Suzuki K Poulose

Hi Greg Please find the updates for coresight and hwtracing subsystems targeting Linux v6.8. Please note that the branch is based on the stable tag, "coresight-fixes-for-v6.7-rc1" (which was merged in v6.7-rc5, on v6.7-rc1). i.e, coresight-next-v6.8....coresight-fixes-for-v6.7-rc1...v6.7-rc1 Kindly pull Suzuki The following changes since commit b85ea95d086471afb4ad062012a4d73cd328fa86: Linux 6.7-rc1 (2023-11-12 16:19:07 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.8 for you to fetch changes up to 60e5f23dc5d68ec01e6dae8f4311230c7d2ccb8a: coresight: ultrasoc-smb: Use guards to cleanup (2023-11-21 11:21:59 +0000) ---------------------------------------------------------------- coresight: Updates for Linux v6.8 Updates for the hwtracing subsystem includes : - Support for CoreSight TPDM DSB set - Support for tuning Cycle count Threshold for CoreSight ETM via perf - Support for TRBE on ACPI based systems - Support for choosing buffer mode in ETR for sysfs mode - Improvements to HiSilicon PTT driver - Cleanups to Ultrasoc SMB driver - Cleanup .remove callback for various Coresight platform drivers - Remove Leo Yan from Reviewers Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Anshuman Khandual (6): coresight: trbe: Add a representative coresight_platform_data for TRBE coresight: trbe: Enable ACPI based TRBE devices coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable coresight: tmc: Make etr buffer mode user configurable from sysfs Bagas Sanjaya (1): Documentation: ABI: coresight-tpdm: Fix Bit[3] description indentation James Clark (2): coresight: Fix crash when Perf and sysfs modes are used concurrently coresight: etm4x: Fix width of CCITMIN field Junhao He (5): hwtracing: hisi_ptt: Add dummy callback pmu::read() coresight: ultrasoc-smb: Fix sleep while close preempt in enable_smb coresight: ultrasoc-smb: Config SMB buffer before register sink coresight: ultrasoc-smb: Fix uninitialized before use buf_hw_base coresight: ultrasoc-smb: Use guards to cleanup Leo Yan (1): MAINTAINERS: Remove myself as a Arm CoreSight reviewer Tao Zhang (14): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support coresight-tpdm: Correct the property name of MSR number Uwe Kleine-König (7): coresight: etm4x: Remove bogous __exit annotation for some functions coresight: dummy: Convert to platform remove callback returning void coresight: etm4x: Convert to platform remove callback returning void coresight: funnel: Convert to platform remove callback returning void coresight: replicator: Convert to platform remove callback returning void coresight: trbe: Convert to platform remove callback returning void coresight: ultrasoc-smb: Convert to platform remove callback returning void Vegard Nossum (1): Documentation: coresight: fix `make refcheckdocs` warning Yicong Yang (4): hwtracing: hisi_ptt: Handle the interrupt in hardirq context hwtracing: hisi_ptt: Don't try to attach a task hwtracing: hisi_ptt: Disable interrupt after trace end hwtracing: hisi_ptt: Optimize the trace data committing .../ABI/testing/sysfs-bus-coresight-devices-tmc | 16 + .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 159 +++++ Documentation/arch/arm64/silicon-errata.rst | 10 + .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + Documentation/trace/coresight/coresight.rst | 6 +- MAINTAINERS | 1 - drivers/hwtracing/coresight/coresight-core.c | 3 + drivers/hwtracing/coresight/coresight-dummy.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 56 +- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- drivers/hwtracing/coresight/coresight-funnel.c | 5 +- drivers/hwtracing/coresight/coresight-replicator.c | 5 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 15 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 111 +++- drivers/hwtracing/coresight/coresight-tmc.h | 3 + drivers/hwtracing/coresight/coresight-tpda.c | 126 +++- drivers/hwtracing/coresight/coresight-tpda.h | 2 + drivers/hwtracing/coresight/coresight-tpdm.c | 718 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 161 +++++ drivers/hwtracing/coresight/coresight-trbe.c | 28 +- drivers/hwtracing/coresight/coresight-trbe.h | 2 + drivers/hwtracing/coresight/ultrasoc-smb.c | 118 ++-- drivers/hwtracing/coresight/ultrasoc-smb.h | 6 +- drivers/hwtracing/ptt/hisi_ptt.c | 33 +- drivers/hwtracing/ptt/hisi_ptt.h | 1 + include/linux/coresight.h | 1 + 27 files changed, 1463 insertions(+), 156 deletions(-)

4 months, 4 weeks

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CoreSight December 2023