This patch series introduces support for CPU cluster local CoreSight components,
including funnel, replicator, and TMC, which reside inside CPU cluster
power domains. These components require special handling due to power
domain constraints.
Unlike system-level CoreSight devices, CPU cluster local components share the
power domain of the CPU cluster. When the cluster enters low-power mode (LPM),
the registers of these components become inaccessible. Importantly, `pm_runtime_get`
calls alone are insufficient to bring the CPU cluster out of LPM, making
standard register access unreliable in such cases.
To address this, the series introduces:
- Device tree bindings for CPU cluster local funnel, replicator, and TMC.
- Introduce a cpumask to record the CPUs belonging to the cluster where the
cpu cluster local component resides.
- Safe register access via smp_call_function_single() on CPUs within the
associated cpumask, ensuring the cluster is power-resident during access.
- Delayed probe support for CPU cluster local components when all CPUs of
this CPU cluster are offline, re-probe the component when any CPU in the
cluster comes online.
- Introduce `cs_mode` to link enable interfaces to avoid the use
smp_call_function_single() under perf mode.
Patch summary:
Patch 1: Adds device tree bindings for CPU cluster funnel/replicator/TMC devices.
Patches 2–3: Add support for CPU cluster funnel.
Patches 4-6: Add support for CPU cluster replicator.
Patches 7-10: Add support for CPU cluster TMC.
Patch 11: Add 'cs_mode' to link enable functions.
Patches 12-13: Add Coresight nodes for APSS debug block for x1e80100 and
fix build issue.
Verification:
This series has been verified on sm8750.
Test steps for delay probe:
1. limit the system to enable at most 6 CPU cores during boot.
2. echo 1 >/sys/bus/cpu/devices/cpu6/online.
3. check whether ETM6 and ETM7 have been probed.
Test steps for sysfs mode:
echo 1 >/sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 >/sys/bus/coresight/devices/etm0/enable_source
echo 1 >/sys/bus/coresight/devices/etm6/enable_source
echo 0 >/sys/bus/coresight/devices/etm0/enable_source
echo 0 >/sys/bus/coresight/devicse/etm6/enable_source
echo 0 >/sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 >/sys/bus/coresight/devices/tmc_etf1/enable_sink
echo 1 >/sys/bus/coresight/devcies/etm0/enable_source
cat /dev/tmc_etf1 >/tmp/etf1.bin
echo 0 >/sys/bus/coresight/devices/etm0/enable_source
echo 0 >/sys/bus/coresight/devices/tmc_etf1/enable_sink
echo 1 >/sys/bus/coresight/devices/tmc_etf2/enable_sink
echo 1 >/sys/bus/coresight/devices/etm6/enable_source
cat /dev/tmc_etf2 >/tmp/etf2.bin
echo 0 >/sys/bus/coresight/devices/etm6/enable_source
echo 0 >/sys/bus/coresight/devices/tmc_etf2/enable_sink
Test steps for sysfs node:
cat /sys/bus/coresight/devices/tmc_etf*/mgmt/*
cat /sys/bus/coresight/devices/funnel*/funnel_ctrl
cat /sys/bus/coresight/devices/replicator*/mgmt/*
Test steps for perf mode:
perf record -a -e cs_etm//k -- sleep 5
Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>
---
Yuanfang Zhang (12):
dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support
coresight-funnel: Add support for CPU cluster funnel
coresight-funnel: Handle delay probe for CPU cluster funnel
coresight-replicator: Add support for CPU cluster replicator
coresight-replicator: Handle delayed probe for CPU cluster replicator
coresight-replicator: Update mgmt_attrs for CPU cluster replicator compatibility
coresight-tmc: Add support for CPU cluster ETF and refactor probe flow
coresight-tmc-etf: Refactor enable function for CPU cluster ETF support
coresight-tmc: Update tmc_mgmt_attrs for CPU cluster TMC compatibility
coresight-tmc: Handle delayed probe for CPU cluster TMC
coresight: add 'cs_mode' to link enable functions
arm64: dts: qcom: x1e80100: add Coresight nodes for APSS debug block
.../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +-
.../arm/arm,coresight-dynamic-replicator.yaml | 22 +-
.../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 885 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 12 +
drivers/hwtracing/coresight/coresight-core.c | 7 +-
drivers/hwtracing/coresight/coresight-funnel.c | 260 +++++-
drivers/hwtracing/coresight/coresight-replicator.c | 343 +++++++-
drivers/hwtracing/coresight/coresight-tmc-core.c | 396 +++++++--
drivers/hwtracing/coresight/coresight-tmc-etf.c | 105 ++-
drivers/hwtracing/coresight/coresight-tmc.h | 10 +
drivers/hwtracing/coresight/coresight-tnoc.c | 3 +-
drivers/hwtracing/coresight/coresight-tpda.c | 3 +-
include/linux/coresight.h | 3 +-
14 files changed, 1912 insertions(+), 182 deletions(-)
---
base-commit: 01f96b812526a2c8dcd5c0e510dda37e09ec8bcd
change-id: 20251016-cpu_cluster_component_pm-ce518f510433
Best regards,
--
Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>
Hi,
On Tue, 28 Oct 2025 at 09:09, Krzysztof Kozlowski <krzk(a)kernel.org> wrote:
>
> On Mon, Oct 27, 2025 at 11:28:03PM -0700, Yuanfang Zhang wrote:
> > Add the following compatible strings to the bindings:
> > - arm,coresight-cpu-funnel
> > - arm,coresight-cpu-replicator
> > - arm,coresight-cpu-tmc
>
These are redundant - the actual hardware has not changed - what has
is how the device is powered up / down on the system
> We see that from the diff. Explain here the hardware instead.
>
> >
> > Each requires 'power-domains' when used.
So why is this not used to adjust the power handling in the driver? Or
another attribute.
Look at the CTI bindings - these can be associated with a CPU or be a
system CTI - we look at the cpu attribute to differentiate, not have
two separate compatibles.
Regards
Mike
> >
> > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>
> > ---
> > .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +++++++++++++++++-----
> > .../arm/arm,coresight-dynamic-replicator.yaml | 22 +++++++++++++++++----
> > .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +++++++++++++++++----
> > 3 files changed, 54 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
> > index b74db15e5f8af2226b817f6af5f533b1bfc74736..8f32d4e3bbb750f5a6262db0032318875739cf81 100644
> > --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
> > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
> > @@ -28,19 +28,32 @@ select:
> > properties:
> > compatible:
> > contains:
> > - const: arm,coresight-dynamic-funnel
> > + enum:
> > + - arm,coresight-dynamic-funnel
> > + - arm,coresight-cpu-funnel
>
> Keep alphabetical sorting. We asked this multiple times already.
>
> > required:
> > - compatible
> >
> > allOf:
> > - $ref: /schemas/arm/primecell.yaml#
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: arm,coresight-cpu-funnel
> > + then:
> > + required:
> > + - power-domains
>
> Just move the allOf to the bottom like in example-schema.
>
> > +
> > properties:
> > compatible:
> > - items:
> > - - const: arm,coresight-dynamic-funnel
> > - - const: arm,primecell
> > -
>
> Why do you remove this?
>
> > + oneOf:
> > + - items:
> > + - const: arm,coresight-dynamic-funnel
> > + - const: arm,primecell
> > + - items:
> > + - const: arm,coresight-cpu-funnel
>
> Hm? Why do you need custom select if this is not primecell? And nothing
> in commit msg explains why this is not primecell anymore.
>
> You have entire commit msg to say something useful, WHY you are doing
> this, WHY you are doing it DIFFERENTLY. Don't say what you did - that's
> obvious, we are capable of reading diffs.
>
> Best regards,
> Krzysztof
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
This series addresses CPU power management issues in the CoreSight
drivers. For easier review, the patches are organized into two
categories:
o Patches 01 ~ 10 focus on CPU power management within the ETM drivers.
These patches fix SMP-safe access to the mode, correct context
synchronization, and refactor the CPU suspend/resume flows.
o Patches 11 ~ 31 extend CPU power management to cover activated paths,
including helpers, links, and sinks. These changes move CPU PM and
hotplug notifiers from the ETMv4 driver into the CoreSight core layer.
Summary:
- Patches 01 ~ 03: Fix device mode access in the SMP mode.
- Patch 04 : A minor fix for polling bit.
- Patches 05 ~ 07: Improve the context synchronization based on the ETM
specification (IHI0064H.b) and Arm ARM (ARM DDI 0487
L.a).
- Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4
driver, in the end, the CPU PM callbacks reuse the
normal enabling and disabling flows.
- Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer.
- Patches 18 ~ 23: Enhance the CTI driver for preparation dynamically
controlling CTI devices in PM flows. This includes
device mode handling in the CTI driver and
distinguishing trace modes (Perf or SysFS). Refactor
the PM notifier and improve locking usage (including
for syscfg).
- Patches 24 ~ 31: Support save and restore context for TRBE and
manages activated paths during CPU idle and
CPU hotplug.
Verification:
This series has been verified on Juno-r0 and r2 platform.
Stress test script:
#!/usr/bin/bash
echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
while true; do
echo 0 > /sys/devices/system/cpu/cpu2/online;
echo 1 > /sys/devices/system/cpu/cpu2/online;
done &
while true; do
echo 1 > /sys/bus/coresight/devices/etm2/enable_source;
echo 0 > /sys/bus/coresight/devices/etm2/enable_source;
done &
Test script with kernel module insmod / rmmod:
#!/bin/bash
modules=(
"coresight"
"coresight_dummy"
"coresight_replicator"
"coresight_tpiu"
"coresight_cpu_debug"
"coresight_etb10"
"coresight_stm"
"coresight_trbe"
"coresight_tmc"
"coresight_ctcu"
"coresight_catu"
"coresight_etm4x"
"coresight_cti"
"coresight_funnel"
"coresight_tnoc"
)
module_dir="/mnt/build/drivers/hwtracing/coresight/"
if [[ "$1" == "in" ]]; then
echo "Inserting modules..."
for mod in "${modules[@]}"; do
modprobe $mod && echo "Loaded $mod" || echo "Failed to load $mod"
done
elif [[ "$1" == "rm" ]]; then
echo "Removing modules..."
# Remove in reverse order to respect dependencies
for (( idx=${#modules[@]}-1 ; idx>=0 ; idx-- )); do
mod="${modules[$idx]}"
echo "Removing $mod..."
rmmod "$mod" && echo "Removed $mod" || echo "Failed to remove $mod"
done
fi
---
Changes in v3:
- Fixed building failure in ETMv3 driver (kernel test robot).
- Refactoring ETMv3 change for checking CPU ID (Levi).
- Fixed NULL pointer issue during CPU idle (James).
- Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James).
- Fixed acquiring mutex in atomic context (James).
- Rebased on the latest coresight-next branch.
- Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c…
Changes in v2:
- Refactored ETMv4 suspend and resume for reusing the normal enabling
and disabling flows (James).
- Used a per-CPU structure to maintain path pointers (James).
- Supported helpers in CPU PM flows (James).
- Fixed the SMP-safe access to device mode.
- Fixed the context synchronization in ETMv4x driver.
- Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a…
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Leo Yan (30):
coresight: Change device mode to atomic type
coresight: etm4x: Always set tracer's device mode on target CPU
coresight: etm3x: Always set tracer's device mode on target CPU
coresight: etm4x: Correct polling IDLE bit
coresight: etm4x: Ensure context synchronization is not ignored
coresight: etm4x: Add context synchronization before enabling trace
coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF
coresight: etm4x: Remove the state_needs_restore flag
coresight: etm4x: Add flag to control single-shot restart
coresight: etm4x: Reuse normal enable and disable logic in CPU idle
coresight: Populate CPU ID into the coresight_device structure
coresight: sysfs: Validate CPU online status for per-CPU sources
coresight: Set per CPU source pointer
coresight: Register CPU PM notifier in core layer
coresight: etm4x: Hook CPU PM callbacks
coresight: Add callback to determine if context save/restore is needed
coresight: etm4x: Remove redundant condition checks in save and restore
coresight: cti: Fix race condition by using device mode
coresight: cti: Introduce CS_MODE_DEBUG mode
coresight: cti: Register PM notifier after data initialization
coresight: cti: Properly handle modes in CPU PM notifiers
coresight: cti: Make spin lock usage consistent
coresight: syscfg: Use spinlock to protect active variables
coresight: Add per-CPU path pointer
coresight: Add 'in_idle' argument to path enable/disable functions
coresight: Control path during CPU idle
coresight: Add PM callbacks for percpu sink
coresight: Take hotplug lock in enable_source_store() for Sysfs mode
coresight: Move CPU hotplug callbacks to core layer
coresight: Manage activated path during CPU hotplug
Yabin Cui (1):
coresight: trbe: Save and restore state across CPU low power state
drivers/hwtracing/coresight/coresight-catu.c | 1 +
drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++--
drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 +
drivers/hwtracing/coresight/coresight-cti-core.c | 69 ++-
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-dummy.c | 1 +
drivers/hwtracing/coresight/coresight-etb10.c | 1 +
drivers/hwtracing/coresight/coresight-etm3x-core.c | 55 ++-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 491 ++++++---------------
drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---
drivers/hwtracing/coresight/coresight-funnel.c | 1 +
drivers/hwtracing/coresight/coresight-replicator.c | 1 +
drivers/hwtracing/coresight/coresight-stm.c | 1 +
drivers/hwtracing/coresight/coresight-syscfg.c | 22 +-
drivers/hwtracing/coresight/coresight-syscfg.h | 2 +
drivers/hwtracing/coresight/coresight-sysfs.c | 10 +
drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
drivers/hwtracing/coresight/coresight-tpda.c | 1 +
drivers/hwtracing/coresight/coresight-tpdm.c | 1 +
drivers/hwtracing/coresight/coresight-tpiu.c | 1 +
drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++
drivers/hwtracing/coresight/ultrasoc-smb.c | 1 +
include/linux/coresight.h | 55 ++-
23 files changed, 687 insertions(+), 515 deletions(-)
---
base-commit: 559d6c380ea0a27e71d0269410301303515e4179
change-id: 20250909-arm_coresight_power_management_fix-139873f942e8
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
All CoreSight compliant components have an implementation defined number
of 0 to 8 claim tag bits in the claim tag registers.
These are used to claim the CoreSight resources by system agents.
ARM recommends implementions have 4 claim tag registers.
The CoreSight drivers implement a 2 claim tag bit protocol to allow
self hosted and external debug agents to manage access to the hardware.
However, if there are less than 2 claim tags available the protocol
incorrectly returns an error on device claim, as no checks are made.
If insufficient claim tags are present in a component then the protocol
must return success on claim / disclaim to allow components to be used
normally.
Changes read the CLAIMSET bits to establish the number of available tags,
and adjust the claim returns accordingly.
Cache the claimtag protocol availablity in the coresight_device to reduce
reads for the main claim/disclaim api.
changes since v1:
1) Added claim tag availability cache into coresight_device when using the
main coresight_claim_device() / coresight_disclaim_device() API.
Applies to coresight/next
Mike Leach (1):
coresight: fix issue where coresight component has no claimtags
drivers/hwtracing/coresight/coresight-core.c | 46 ++++++++++++++++++--
drivers/hwtracing/coresight/coresight-priv.h | 10 +++++
include/linux/coresight.h | 15 +++++++
3 files changed, 68 insertions(+), 3 deletions(-)
--
2.32.0
On 27/10/2025 10:43, Yeoreum Yun wrote:
> Hi Suzuki,
>> On 24/10/2025 17:45, Leo Yan wrote:
>>> As recommended in section 4.3.7 "Synchronization of register updates" of
>>> ARM IHI0064H.b, a self-hosted trace analyzer should always executes an
>>> ISB instruction after programming the trace unit registers.
>>>
>>> An ISB works as a context synchronization event; a DSB is not required.
>>> Removes the redundant barrier in the enabling flow.
>>
>> It is required for MMIO based instances and must be retained.
>
> I think it seems fine. since the the etm4x device mmio is mapped as
> Device-nGnRE and according to the section Leo mention:
>
> Synchronization when using the memory-mapped interface
> ..
> When disabling or enabling the trace unit, the trace analyzer must poll TRCSTATR to check the trace unit is either
> idle or not idle, as described in Use of the trace unit main enable bit on page 4-169:
> • When the memory is marked as Device-nGnRE or stronger.
> — Write to enable or disable the trace unit.
> — Poll TRCSTATR to ensure the previous write has completed.
> — Execute an ISB operation.
>
> Therefore, we can omit the dsb in here.
You are right, to be precise, as long as we quote the following, I am fine.
Section 4.3.7, Synchronization when using the memory-mapped interface -
When using the memory-mapped interface to program the trace unit, the
trace analyzer must ensure that writes have completed, to ensure that
the trace unit is fully programmed and either enabled or disabled.
• If the memory marked is as Device-nGnRE or stronger, read back the
value of any register in the trace unit. This relies on peripheral
coherence order defined in the Arm architecture.
Suzuki
>
> [...]
>
> Thanks.
>
> --
> Sincerely,
> Yeoreum Yun
This series is extracted from the CoreSight power management fixes and
refactoring [1], focusing on ETMv3/4 power management. The remaining
parts will be sent out separately. Hopefully, this makes things easier
for us to review and merge.
Compared to the previous version, only one new patch has been added — to
retain the sequencer state for ETMv4. No other changes are included.
This series has been verified on Juno-r2 platform.
[1] https://lore.kernel.org/linux-arm-kernel/20250915-arm_coresight_power_manag…
---
Changes in v4:
- Added patch 10 for retaining sequencer state in ETMv4 driver (Mike).
- Added Mike's review tags.
- Added James' test tags.
- Link to v3: https://lore.kernel.org/r/20250915-arm_coresight_power_management_fix-v3-0-…
Changes in v3:
- Fixed building failure in ETMv3 driver (kernel test robot).
- Refactoring ETMv3 change for checking CPU ID (Levi).
- Fixed NULL pointer issue during CPU idle (James).
- Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James).
- Fixed acquiring mutex in atomic context (James).
- Rebased on the latest coresight-next branch.
- Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c…
Changes in v2:
- Refactored ETMv4 suspend and resume for reusing the normal enabling
and disabling flows (James).
- Used a per-CPU structure to maintain path pointers (James).
- Supported helpers in CPU PM flows (James).
- Fixed the SMP-safe access to device mode.
- Fixed the context synchronization in ETMv4x driver.
- Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a…
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Leo Yan (11):
coresight: Change device mode to atomic type
coresight: etm4x: Always set tracer's device mode on target CPU
coresight: etm3x: Always set tracer's device mode on target CPU
coresight: etm4x: Correct polling IDLE bit
coresight: etm4x: Ensure context synchronization is not ignored
coresight: etm4x: Add context synchronization before enabling trace
coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF
coresight: etm4x: Remove the state_needs_restore flag
coresight: etm4x: Add flag to control single-shot restart
coresight: etm4x: Retain sequencer state
coresight: etm4x: Reuse normal enable and disable logic in CPU idle
drivers/hwtracing/coresight/coresight-etm3x-core.c | 59 ++--
drivers/hwtracing/coresight/coresight-etm4x-core.c | 372 +++++++--------------
drivers/hwtracing/coresight/coresight-etm4x.h | 62 ----
include/linux/coresight.h | 25 +-
4 files changed, 175 insertions(+), 343 deletions(-)
---
base-commit: 6fab32bb6508abbb8b7b1c5498e44f0c32320ed5
change-id: 20250909-arm_coresight_power_management_fix-139873f942e8
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
On 27/10/2025 01:14, Jie Gan wrote:
>
>
> On 8/27/2025 6:55 PM, Jie Gan wrote:
>> Patchset 1 introduces configuration of the cross-trigger registers with
>> appropriate values to enable proper generation of cross-trigger packets.
>>
>> Patchset 2 introduces a logic to configure the TPDA_SYNCR register,
>> which determines the frequency of ASYNC packet generation. These packets
>> assist userspace tools in accurately identifying each valid packet.
>>
>> Patchset 3 introduces a sysfs node to initiate a flush request for the
>> specific port, forcing the data to synchronize and be transmitted to the
>> sink device.
>>
>
> Gentle reminder.
Please could you fix the dates and version to v6.19 ?
Suzuki
>
> Thanks,
> Jie
>
>> Changes in V3:
>> 1. Optimizing codes according to James's comment.
>> Link to V2 - https://lore.kernel.org/all/20250827042042.6786-1-
>> jie.gan(a)oss.qualcomm.com/
>>
>> Changes in V2:
>> 1. Refactoring the code based on James's comment for optimization.
>> Link to V1 - https://lore.kernel.org/all/20250826070150.5603-1-
>> jie.gan(a)oss.qualcomm.com/
>>
>> Tao Zhang (3):
>> coresight: tpda: add sysfs nodes for tpda cross-trigger configuration
>> coresight: tpda: add logic to configure TPDA_SYNCR register
>> coresight: tpda: add sysfs node to flush specific port
>>
>> .../testing/sysfs-bus-coresight-devices-tpda | 50 ++++
>> drivers/hwtracing/coresight/coresight-tpda.c | 278 ++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 33 ++-
>> 3 files changed, 360 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-
>> devices-tpda
>>
>