I've gotten stuck a few times with unusable Coresight after a warm boot
due to lingering claim tags, especially when testing the Coresight
panic patchsets.
This change does some tidy ups, adds some debug messages and clears the
self hosted claim tag on probe. The last two commits are unrelated
tidyups but they touch some of the same functions so to avoid extra
conflicts I'm including them here.
This gets as far as fixing the claim tag issue, but there is some other
state not being cleared on probe that results in the following error.
This can be fixed up as a later change:
coresight tmc_etf0: timeout while waiting for TMC to be Ready
coresight tmc_etf0: Failed to enable : TMC is not ready
James Clark (7):
coresight: Rename coresight_{set,clear}_claim_tags()
coresight: Convert disclaim functions to take a struct cs_access
coresight: Only check bottom two claim bits
coresight: Add claim tag warnings and debug messages
coresight: Clear self hosted claim tag on probe
coresight: Remove inlines from static function definitions
coresight: Remove extern from function declarations
drivers/hwtracing/coresight/coresight-catu.c | 14 +-
drivers/hwtracing/coresight/coresight-core.c | 132 +++++++++++-------
.../hwtracing/coresight/coresight-cti-core.c | 8 +-
drivers/hwtracing/coresight/coresight-etb10.c | 6 +-
drivers/hwtracing/coresight/coresight-etm.h | 6 +-
.../coresight/coresight-etm3x-core.c | 32 ++---
.../coresight/coresight-etm3x-sysfs.c | 8 +-
.../coresight/coresight-etm4x-core.c | 12 +-
.../coresight/coresight-etm4x-sysfs.c | 4 +-
.../hwtracing/coresight/coresight-funnel.c | 4 +-
.../hwtracing/coresight/coresight-platform.c | 26 ++--
drivers/hwtracing/coresight/coresight-priv.h | 20 +--
.../coresight/coresight-replicator.c | 7 +-
drivers/hwtracing/coresight/coresight-stm.c | 6 +-
.../coresight/coresight-syscfg-configfs.c | 2 +-
.../hwtracing/coresight/coresight-tmc-core.c | 9 +-
.../hwtracing/coresight/coresight-tmc-etf.c | 8 +-
.../hwtracing/coresight/coresight-tmc-etr.c | 20 ++-
drivers/hwtracing/coresight/coresight-trbe.c | 18 +--
include/linux/coresight.h | 32 ++---
20 files changed, 209 insertions(+), 165 deletions(-)
--
2.34.1
Previously the sink had to be specified, but now it auto selects one by
default. Including a sink in the examples causes issues when copy
pasting the command because it might not work if that sink isn't
present. Remove the sink from all the basic examples and create a new
section specifically about overriding the default one.
Make the text a but more concise now that it's in the advanced section,
and similarly for removing the old kernel advice.
Signed-off-by: James Clark <james.clark(a)linaro.org>
---
Documentation/trace/coresight/coresight.rst | 41 ++++++++-----------
.../userspace-api/perf_ring_buffer.rst | 4 +-
2 files changed, 18 insertions(+), 27 deletions(-)
diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst
index d4f93d6a2d63..806699871b80 100644
--- a/Documentation/trace/coresight/coresight.rst
+++ b/Documentation/trace/coresight/coresight.rst
@@ -462,44 +462,35 @@ queried by the perf command line tool:
cs_etm// [Kernel PMU event]
- linaro@linaro-nano:~$
-
Regardless of the number of tracers available in a system (usually equal to the
amount of processor cores), the "cs_etm" PMU will be listed only once.
A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is
-listed along with configuration options within forward slashes '/'. Since a
-Coresight system will typically have more than one sink, the name of the sink to
-work with needs to be specified as an event option.
-On newer kernels the available sinks are listed in sysFS under
+provided along with configuration options within forward slashes '/' (see
+`Config option formats`_).
+
+Advanced Perf framework usage
+-----------------------------
+
+Sink selection
+~~~~~~~~~~~~~~
+
+An appropriate sink will be selected automatically for use with Perf, but since
+there will typically be more than one sink, the name of the sink to use may be
+specified as a special config option prefixed with '@'.
+
+The available sinks are listed in sysFS under
($SYSFS)/bus/event_source/devices/cs_etm/sinks/::
root@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls
tmc_etf0 tmc_etr0 tpiu0
-On older kernels, this may need to be found from the list of coresight devices,
-available under ($SYSFS)/bus/coresight/devices/::
-
- root:~# ls /sys/bus/coresight/devices/
- etm0 etm1 etm2 etm3 etm4 etm5 funnel0
- funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
-As mentioned above in section "Device Naming scheme", the names of the devices could
-look different from what is used in the example above. One must use the device names
-as it appears under the sysFS.
-
-The syntax within the forward slashes '/' is important. The '@' character
-tells the parser that a sink is about to be specified and that this is the sink
-to use for the trace session.
-
More information on the above and other example on how to use Coresight with
the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub
repository [#third]_.
-Advanced perf framework usage
------------------------------
-
AutoFDO analysis using the perf tools
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -508,7 +499,7 @@ perf can be used to record and analyze trace of programs.
Execution can be recorded using 'perf record' with the cs_etm event,
specifying the name of the sink to record to, e.g::
- perf record -e cs_etm/@tmc_etr0/u --per-thread
+ perf record -e cs_etm//u --per-thread
The 'perf report' and 'perf script' commands can be used to analyze execution,
synthesizing instruction and branch events from the instruction trace.
@@ -572,7 +563,7 @@ sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tuto
Bubble sorting array of 30000 elements
5910 ms
- $ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort
+ $ perf record -e cs_etm//u --per-thread taskset -c 2 ./sort
Bubble sorting array of 30000 elements
12543 ms
[ perf record: Woken up 35 times to write data ]
diff --git a/Documentation/userspace-api/perf_ring_buffer.rst b/Documentation/userspace-api/perf_ring_buffer.rst
index bde9d8cbc106..dc71544532ce 100644
--- a/Documentation/userspace-api/perf_ring_buffer.rst
+++ b/Documentation/userspace-api/perf_ring_buffer.rst
@@ -627,7 +627,7 @@ regular ring buffer.
AUX events and AUX trace data are two different things. Let's see an
example::
- perf record -a -e cycles -e cs_etm/@tmc_etr0/ -- sleep 2
+ perf record -a -e cycles -e cs_etm// -- sleep 2
The above command enables two events: one is the event *cycles* from PMU
and another is the AUX event *cs_etm* from Arm CoreSight, both are saved
@@ -766,7 +766,7 @@ only record AUX trace data at a specific time point which users are
interested in. E.g. below gives an example of how to take snapshots
with 1 second interval with Arm CoreSight::
- perf record -e cs_etm/@tmc_etr0/u -S -a program &
+ perf record -e cs_etm//u -S -a program &
PERFPID=$!
while true; do
kill -USR2 $PERFPID
--
2.34.1
On 2/26/2025 7:07 PM, Krzysztof Kozlowski wrote:
> On 26/02/2025 11:52, Yuanfang Zhang wrote:
>>
>>
>> On 2/22/2025 6:47 PM, Krzysztof Kozlowski wrote:
>>> On 21/02/2025 08:40, Yuanfang Zhang wrote:
>>>> Adds new coresight-tnoc.yaml file describing the bindings required
>>>> to define Trace NOC in the device trees.
>>>>
>>>> Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
>>>
>>>
>>> So you just sent the same v1, ignoring previous review. That's not how
>>> it works.
>>>
>> sorry for this incorrect process. because i just update --to-cc list and no other
>> change, i forced the version to V1, hoped it would work like resend,
>> but the result was not as expected.
>
>
> But you got feedback, so why resending without implementing it? That's
> the problem, not you labeled/not-labeled it as resend.
>
got it, will implement it in next patch.
> Best regards,
> Krzysztof
Version 1.5.6 is now release.
Contains build fixes and documentation upates
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK