Besides managing tracers (ETM) in CPU PM and hotplug flows, the
CoreSight framework is found the issues below:
Firstly, on some hardware platforms, CoreSight links (e.g., funnels and
replicators, etc) reside in a cluster power domain. If the cluster is
powered off, the link components also will lose their context. In this
case, Arm CoreSight drivers report errors when detect unpaired self-host
claim tags.
Secondly, if a path has been activated from per CPU's tracer (ETM) to
links and a sink in Sysfs mode, then when the CPU is hot-plugged off,
only the associated ETM will be disabled. Afterwards, the links and the
sink always keep on and no chance to be disabled.
The last issue was reported by Yabin Cui (Google) that the TRBE driver
misses to save and restore context during CPU low power states. As a
result, it may cause hardware lockup issue on some devices.
To resolve the power management issues, this series extends CPU power
management to cover the entire activated path, including links and
sinks. It moves CPU PM and hotplug notifiers from the ETMv4 driver to
the CoreSight core layer. The core layer has sufficient info to
maintain activated paths and can traverse the entire path to manipulate
CoreSight modules accordingly.
Patch 01 is to fix a bug in ETMv4 save and restore callbacks.
Patches 02 ~ 06 move CPU PM code from ETMv4 driver to the core layer, and
extends to maintain activated paths and control links.
Patches 07 and 08 support save and restore context for per-CPU sink
(TRBE). Note, for avoid long latency, system level's sinks in an
activated path are not touched during CPU suspend and resume.
Patches 09 ~ 11 move CPU hotplug notifier from ETMv4 driver to the core
layer. The entire path will be controlled if the corresponding CPU is
hot-plugged on or off.
This series has been verified on Hikey960 for CPUIdle and hotplug. And
it is tested on FVP for verifying TRBE with idle states.
Leo Yan (10):
coresight: etm4x: Control the trace unit in CPU suspend
coresight: Set per CPU source pointer
coresight: Register CPU PM notifier in core layer
coresight: etm4x: Hook CPU PM callbacks
coresight: Save activated path into source device
coresight: Control path during CPU PM
coresight: Add PM callbacks in sink operation
coresight: Take hotplug lock in enable_source_store() for Sysfs mode
coresight: Move CPU hotplug callbacks to core layer
coresight: Manage activated paths during CPU hotplug
Yabin Cui (1):
coresight: trbe: Save and restore state across CPU low power state
drivers/hwtracing/coresight/coresight-core.c | 252 +++++++++++++++++++++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +
drivers/hwtracing/coresight/coresight-etm4x-core.c | 133 ++++++----------------
drivers/hwtracing/coresight/coresight-priv.h | 1 +
drivers/hwtracing/coresight/coresight-sysfs.c | 12 +-
drivers/hwtracing/coresight/coresight-trbe.c | 65 +++++++++++
include/linux/coresight.h | 11 ++
7 files changed, 375 insertions(+), 101 deletions(-)
--
2.34.1
Cc: coresight lists, Leo, James, Mike L
Hello !
Thanks for the report ! In the future, please use
scripts/get_maintainer.pl for the clear list of people/list
for reporting issues.
Response inline, below.
On 20/06/2025 08:21, Keita Morisaki wrote:
> Hello folks,
>
> I am writing to report a WARN_ON message I'm encountering in the
> CoreSight driver on a multi-core ARM system running a 6.12-based kernel.
> The warning appears consistently when disabling an Embedded Trace
> Extension (ETE) source after it has been active. The issue is not
> reproducible when CPUidle is disabled.
>
> The problem occurs because the driver assumes the CoreSight claim
> register is persistent, but it could be reset by the CPUidle power
> management flow. The section B2.3.2 of Arm CoreSight Architecture
> Specification v3.0[1] indicates that the claim register must reset at
> “reset”. A CPU power-up from an idle state can trigger a Cold reset,
> which might explain this behavior.
>
> My ftrace analysis confirms this. I traced the only two functions that
> modify the claim state: coresight_set_claim_tags (which sets the claim)
> and coresight_clear_claim_tags (which is the only part of the kernel
> that writes to CLAIMCLR). The trace shows the claim being set, followed
> by a CPUidle transition, but no subsequent call to
> coresight_clear_claim_tags.
>
> Here are the steps to reproduce the issue:
>
> modprobecoresight_etm4x
>
> # Enable any relevant sink
>
> echo1>/sys/bus/coresight/devices/ete0/enable_source
>
> echo0>/sys/bus/coresight/devices/ete0/enable_source
>
>
> Here is a relevant snippet from the ftrace log that illustrates the
> sequence:
>
> #tracer:function_graph
>
> #
>
> #CPUDURATIONFUNCTIONCALLS
>
> #|||||||
>
> 0)|coresight_claim_device_unlocked[coresight](){
>
> 0)3.750us|coresight_set_claim_tags[coresight]();//Claimissethere
>
> 0)+20.260us|}
>
> 0)|/*psci_domain_idle_enter:cpu_id=0state={Our PSCI parameter value}*///
> CPUgoesidle
>
> 0)|/*psci_domain_idle_exit:cpu_id=0state={Our PSCI parameter value}*///
> CPUwakesup,causingColdreset
>
> ...
>
> 0)(a)309346.3us|coresight_disclaim_device_unlocked[coresight]();//
> TriggersWARN_ON
>
>
> The following WARN_ON [2] is printed because the CLAIMCLR register has
> already been reset at the time coresight_disclaim_device_unlocked is
> called, contrary to the driver's expectation.
>
We have the ETM driver performing the save/restore of ETM context during
a CPUidle. This is only done when the ETM/ETE is described to be loosing
context over PM operation. If this is not done (via DT), the driver
doesn't do anything. This could be problematic. Could you try adding:
"arm,coresight-loses-context-with-cpu"
property to the ETE nodes and see if it makes a difference ?
Kind regards
Suzuki
[0]
https://elixir.bootlin.com/linux/v6.12/source/Documentation/devicetree/bind…
> [416.354181][C0]WARNING:CPU:0PID:0atdrivers/hwtracing/coresight/
> coresight-core.c:187coresight_disclaim_device_unlocked+0x84/0x9c[coresight]
>
> [416.535454][C0]Calltrace:
>
> [416.538606][C0]coresight_disclaim_device_unlocked+0x84/0x9c[coresight]
>
> [416.549359][C0]etm4_disable_hw+0x2d8/0x374[coresight_etm4x]
>
> [416.623310][C0]do_idle+0x1d4/0x264
>
> (Note on tracing: To get this detailed trace, I made two modifications
> to the kernel. First, since the trace_psci_domain_idle_enter/exit events
> are not available in kernel 6.12, I cherry-picked the upstream patch
> 7b7644831e72 [3] to add them. Second, to specifically trace the claim
> functions, I temporarily replaced their inline compiler hints with
> noinline.)
>
> Given the evidence, it appears the driver's assumption that the claim
> register is persistent across CPU power states is incorrect and may need
> to be addressed.
>
> Could you please provide your guidance on this?
>
> Thank you for your time and assistance.
>
> [1] https://developer.arm.com/documentation/ihi0029/latest/ <https://
> developer.arm.com/documentation/ihi0029/latest/>_
> _[2] https://elixir.bootlin.com/linux/v6.12/source/drivers/hwtracing/
> coresight/coresight-core.c#L187 <https://elixir.bootlin.com/linux/v6.12/
> source/drivers/hwtracing/coresight/coresight-core.c#L187>_
> _[3] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/
> linux.git/commit/?id=7b7644831e7276f52a233ec685d13c965fff09d9 <https://
> web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?
> id=7b7644831e7276f52a233ec685d13c965fff09d9>
>
> Best regards,
> Keita
This patchset builds upon Yicong's previous patches [1].
Introducing fix two race issues found by using TMC-ETR and CATU, Two
cleanups found when debugging the issues.
[1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@…
---
Changes in v2:
- Updated the commit of patch2.
- Rebase to v6.16-rc1
Junhao He (1):
coresight: tmc: refactor the tmc-etr mode setting to avoid race
conditions
Yicong Yang (2):
coresight: tmc: Add missing doc of tmc_drvdata::reading
coresight: tmc: Decouple the perf buffer allocation from sysfs mode
.../hwtracing/coresight/coresight-tmc-etr.c | 102 +++++++++---------
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
2 files changed, 53 insertions(+), 50 deletions(-)
--
2.33.0
On 19/06/2025 4:07 pm, Chelsy Ratnawat wrote:
> Replace calls to scnprintf() with sysfs_emit() in sysfs show functions.
> These helpers are preferred in sysfs callbacks because they automatically
> handle buffer sizing (PAGE_SIZE) and improve safety and readability.
>
> Signed-off-by: Chelsy Ratnawat <chelsyratnawat2001(a)gmail.com>
> ---
> .../hwtracing/coresight/coresight-etm-perf.c | 4 +-
> .../coresight/coresight-etm3x-sysfs.c | 2 +-
> .../coresight/coresight-etm4x-sysfs.c | 108 +++++++++---------
> drivers/hwtracing/coresight/coresight-stm.c | 8 +-
There's two missing from coresight-sysfs.c. Might as well change those
too while were here.
With those changed:
Reviewed-by: James Clark <james.clark(a)linaro.org>
A branch ocsd-main-v1.6.1-rc1 has been released on the OpenCSD github site
This contains a number of bugfixes for issues relating to ETMv4 ETE
speculative trace. See readme for further information.
This has been released to allow for testing and feedback.
Known issues outstanding:
a) TINFO logging has minor issue on periodic TINFO elements.
b) ETMv3 / PTM regression testss failing on return stack tests. Under
investigation as this code is not part of the update.
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
This series polishes the code to address warnings reported by the smatch
static checker.
Smatch reports a error "Function too hairy" for etm4x_sysreg_read() and
etm4x_sysreg_write(). This is a trade off to avoid large code blocks,
the implementation encapsulates logic using nested macros. But this is
not friendly to static checker. For now, the code will be kept as is.
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Leo Yan (2):
coresight: stm: Remove redundant NULL checks
coresight: perf: Use %px for printing pointers
drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++--
drivers/hwtracing/coresight/coresight-stm.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164
change-id: 20250611-arm_cs_fix_smatch_warning_v1-6c2b5e78e38a
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
The Trace Network On Chip (TNOC) is an integration hierarchy which is a
hardware component that integrates the functionalities of TPDA and
funnels. It collects trace from subsystems and transfers it to coresight
sink.
In addition to the generic TNOC mentioned above, there is also a special type
of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect
TNOC doesn't need ATID. Its primary function is to connect the source of
subsystems to the Aggregator TNOC. Its driver is different from this patch and
will describe it and upstream its driver separately.
Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
---
Changes in v9:
- Mention the binding is only for Aggregator TNOC.
- Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com
Changes in v8:
- Add sysfs node to expose atid.
- Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com
Changes in v7:
- Move the content in header file into coresight-tnoc.c.
- Use scoped_guard() to replace spin_lock().
- Invoke coresight_trace_id_put_system_id() for registration failure.
- Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com
Changes in v6:
- Add a newline after return statements.
- Use 'x &= foo' to replace 'x = x & foo'.
- Use 'x |= foo' to replace 'x = x | foo'.
- Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com
Changes in v5:
- update cover-letter to describe the Interconnect TNOC.
- Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com
Changes in v4:
- Fix dt_binding warning.
- update mask of trace_noc amba_id.
- Modify driver comments.
- rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL.
- Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com
Changes in v3:
- Remove unnecessary sysfs nodes.
- update commit messages.
- Use 'writel' instead of 'write_relaxed' when writing to the register for the last time.
- Add trace_id ops.
- Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici…
Changes in v2:
- Modified the format of DT binging file.
- Fix compile warnings.
- Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com
---
Yuanfang Zhang (2):
dt-bindings: arm: Add device Trace Network On Chip definition
coresight: add coresight Trace Network On Chip driver
.../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++
drivers/hwtracing/coresight/Kconfig | 13 ++
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++
4 files changed, 369 insertions(+)
---
base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11
change-id: 20250403-trace-noc-f8286b30408e
Best regards,
--
Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
The Trace Network On Chip (TNOC) is an integration hierarchy which is a
hardware component that integrates the functionalities of TPDA and
funnels. It collects trace from subsystems and transfers it to coresight
sink.
In addition to the generic TNOC mentioned above, there is also a special type
of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect
TNOC doesn't need ATID. Its primary function is to connect the source of
subsystems to the Aggregator TNOC. Its driver is different from this patch and
will describe it and upstream its driver separately.
Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
---
Changes in v10:
- Rebase to coresight/next branch.
- Link to v9: https://lore.kernel.org/r/20250611-trace-noc-v9-0-4322d4cf8f4b@quicinc.com
Changes in v9:
- Mention the binding is only for Aggregator TNOC.
- Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com
Changes in v8:
- Add sysfs node to expose atid.
- Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com
Changes in v7:
- Move the content in header file into coresight-tnoc.c.
- Use scoped_guard() to replace spin_lock().
- Invoke coresight_trace_id_put_system_id() for registration failure.
- Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com
Changes in v6:
- Add a newline after return statements.
- Use 'x &= foo' to replace 'x = x & foo'.
- Use 'x |= foo' to replace 'x = x | foo'.
- Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com
Changes in v5:
- update cover-letter to describe the Interconnect TNOC.
- Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com
Changes in v4:
- Fix dt_binding warning.
- update mask of trace_noc amba_id.
- Modify driver comments.
- rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL.
- Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com
Changes in v3:
- Remove unnecessary sysfs nodes.
- update commit messages.
- Use 'writel' instead of 'write_relaxed' when writing to the register for the last time.
- Add trace_id ops.
- Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici…
Changes in v2:
- Modified the format of DT binging file.
- Fix compile warnings.
- Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com
---
Yuanfang Zhang (2):
dt-bindings: arm: Add device Trace Network On Chip definition
coresight: add coresight Trace Network On Chip driver
.../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++
drivers/hwtracing/coresight/Kconfig | 12 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++
4 files changed, 368 insertions(+)
---
base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164
change-id: 20250403-trace-noc-f8286b30408e
Best regards,
--
Yuanfang Zhang <quic_yuanfang(a)quicinc.com>