Change since V7:
1. Update the conflict when apply to coresight next.
2. Update the Date and version in ABI file.
V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.…
Change since V6:
1. Update the date and verison in ABI file.
Change since V5:
1. Update the kernel version of ABI files.
2. Add link of different patch versions.
V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319…
Change since V4:
1. Add label in DT and add label sysfs node for each coresight device.
V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268…
Change since V3:
1. Change device-name to arm,cs-dev-name.
2. Add arm,cs-dev-name to only CTI and sources' dt-binding.
V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628…
Change since V2:
1. Fix the error in coresight core.
drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers
2. Fix the warning when run dtbinding check.
Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition
V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265…
Change since V1:
1. Change coresight-name to device name.
2. Add the device-name in coresight dt bindings.
V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.…
Mao Jinlong (2):
dt-bindings: arm: Add label in the coresight components
coresight: Add label sysfs node support
.../testing/sysfs-bus-coresight-devices-cti | 6 ++++
.../sysfs-bus-coresight-devices-funnel | 6 ++++
.../testing/sysfs-bus-coresight-devices-tpdm | 6 ++++
.../bindings/arm/arm,coresight-cti.yaml | 6 ++++
.../arm/arm,coresight-dummy-sink.yaml | 6 ++++
.../arm/arm,coresight-dummy-source.yaml | 6 ++++
.../arm/arm,coresight-dynamic-funnel.yaml | 6 ++++
.../arm/arm,coresight-dynamic-replicator.yaml | 6 ++++
.../arm/arm,coresight-static-funnel.yaml | 6 ++++
.../arm/arm,coresight-static-replicator.yaml | 6 ++++
.../bindings/arm/arm,coresight-tmc.yaml | 6 ++++
.../bindings/arm/qcom,coresight-tpda.yaml | 6 ++++
.../bindings/arm/qcom,coresight-tpdm.yaml | 6 ++++
drivers/hwtracing/coresight/coresight-sysfs.c | 32 +++++++++++++++++++
14 files changed, 110 insertions(+)
--
2.17.1
This series addresses CPU power management issues in the CoreSight
drivers. For easier review, the patches are organized into two
categories:
o Patches 01 ~ 10 focus on CPU power management within the ETM drivers.
These patches fix SMP-safe access to the mode, correct context
synchronization, and refactor the CPU suspend/resume flows.
o Patches 11 ~ 28 extend CPU power management to cover activated paths,
including helpers, links, and sinks. These changes move CPU PM and
hotplug notifiers from the ETMv4 driver into the CoreSight core layer.
Summary of Changes:
- Patches 01 ~ 03: Fix device mode access in the SMP mode.
- Patch 04 : A minor fix for polling bit.
- Patches 05 ~ 07: Improve the context synchronization based on the ETM
specification (IHI0064H.b) and Arm ARM (ARM DDI 0487
L.a).
- Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4
driver, in the end, the CPU PM callbacks reuse the
normal enabling and disabling flows.
- Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer.
- Patches 18 ~ 25: Enhance device mode handling in the CTI driver,
distinguishes debug mode from trace modes (Perf or
SysFS mode). Extend support activated paths during
CPU idle. Support save and restore context for
per-CPU sink (TRBE).
- Patches 26 ~ 28: Move CPU hotplug notifier from the ETMv4 driver to
the core layer. The full path is now managed in CPU
hotplug.
Verification:
This series has been verified on the following platforms:
- Hikey960, Juno-r0 and Juno-r2:
Note that the firmware on Hikey960 and Juno-r0 is unstable. While no
CoreSight failures were observed, but the CPU hotplug or CPU idle
itself may fail intermittently.
Juno-r2 is much stable and can pass 24+ hours stress test.
- FVP RevC: Verified TRBE changes.
Stress test script:
#!/usr/bin/bash
echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
while true; do
echo 0 > /sys/devices/system/cpu/cpu2/online;
echo 1 > /sys/devices/system/cpu/cpu2/online;
done &
while true; do
echo 1 > /sys/bus/coresight/devices/etm2/enable_source;
echo 0 > /sys/bus/coresight/devices/etm2/enable_source;
done &
---
Changes in v2:
- Refactored ETMv4 suspend and resume for reusing the normal enabling
and disabling flows (James).
- Used a per-CPU structure to maintain path pointers (James).
- Supported helpers in CPU PM flows (James).
- Fixed the SMP-safe access to device mode.
- Fixed the context synchronization in ETMv4x driver.
- Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a…
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Leo Yan (27):
coresight: Change device mode to atomic type
coresight: etm4x: Always set tracer's device mode on target CPU
coresight: etm3x: Always set tracer's device mode on target CPU
coresight: etm4x: Correct polling IDLE bit
coresight: etm4x: Ensure context synchronization is not ignored
coresight: etm4x: Add context synchronization before enabling trace
coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF
coresight: etm4x: Remove the state_needs_restore flag
coresight: etm4x: Add flag to control single-shot restart
coresight: etm4x: Reuse normal enable and disable logic in CPU idle
coresight: Populate CPU ID into the coresight_device structure
coresight: sysfs: Validate CPU online status for per-CPU sources
coresight: Set per CPU source pointer
coresight: Register CPU PM notifier in core layer
coresight: etm4x: Hook CPU PM callbacks
coresight: Add callback to determine if context save/restore is needed
coresight: etm4x: Remove redundant condition checks in save and restore
coresight: cti: Fix race condition by using device mode
coresight: cti: Introduce CS_MODE_DEBUG mode
coresight: cti: Properly handle modes in CPU PM notifiers
coresight: Add per-CPU path pointer
coresight: Add 'in_idle' argument to path enable/disable functions
coresight: Control path during CPU idle
coresight: Add PM callbacks for percpu sink
coresight: Take hotplug lock in enable_source_store() for Sysfs mode
coresight: Move CPU hotplug callbacks to core layer
coresight: Manage activated path during CPU hotplug
Yabin Cui (1):
coresight: trbe: Save and restore state across CPU low power state
drivers/hwtracing/coresight/coresight-catu.c | 1 +
drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++--
drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 +
drivers/hwtracing/coresight/coresight-cti-core.c | 40 +-
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-dummy.c | 1 +
drivers/hwtracing/coresight/coresight-etb10.c | 1 +
drivers/hwtracing/coresight/coresight-etm3x-core.c | 61 ++-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 488 ++++++---------------
drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---
drivers/hwtracing/coresight/coresight-funnel.c | 1 +
drivers/hwtracing/coresight/coresight-replicator.c | 1 +
drivers/hwtracing/coresight/coresight-stm.c | 1 +
drivers/hwtracing/coresight/coresight-sysfs.c | 10 +
drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
drivers/hwtracing/coresight/coresight-tpda.c | 1 +
drivers/hwtracing/coresight/coresight-tpdm.c | 1 +
drivers/hwtracing/coresight/coresight-tpiu.c | 1 +
drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++
drivers/hwtracing/coresight/ultrasoc-smb.c | 1 +
include/linux/coresight.h | 55 ++-
21 files changed, 665 insertions(+), 487 deletions(-)
---
base-commit: 66701750d5565c574af42bef0b789ce0203e3071
change-id: 20250611-arm_cs_pm_fix_v3-f4ae29bb7d81
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
The Trace Network On Chip (TNOC) is an integration hierarchy which is a
hardware component that integrates the functionalities of TPDA and
funnels. It collects trace from subsystems and transfers it to coresight
sink.
In addition to the generic TNOC mentioned above, there is also a special type
of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect
TNOC doesn't need ATID. Its primary function is to connect the source of
subsystems to the Aggregator TNOC. Its driver is different from this patch and
will describe it and upstream its driver separately.
Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
---
Changes in v11:
- reorder of trace ID release and device unregister.
- Link to v10: https://lore.kernel.org/r/20250611-trace-noc-v10-0-a83b5c63da34@quicinc.com
Changes in v10:
- Rebase to coresight/next branch.
- Link to v9: https://lore.kernel.org/r/20250611-trace-noc-v9-0-4322d4cf8f4b@quicinc.com
Changes in v9:
- Mention the binding is only for Aggregator TNOC.
- Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com
Changes in v8:
- Add sysfs node to expose atid.
- Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com
Changes in v7:
- Move the content in header file into coresight-tnoc.c.
- Use scoped_guard() to replace spin_lock().
- Invoke coresight_trace_id_put_system_id() for registration failure.
- Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com
Changes in v6:
- Add a newline after return statements.
- Use 'x &= foo' to replace 'x = x & foo'.
- Use 'x |= foo' to replace 'x = x | foo'.
- Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com
Changes in v5:
- update cover-letter to describe the Interconnect TNOC.
- Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com
Changes in v4:
- Fix dt_binding warning.
- update mask of trace_noc amba_id.
- Modify driver comments.
- rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL.
- Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com
Changes in v3:
- Remove unnecessary sysfs nodes.
- update commit messages.
- Use 'writel' instead of 'write_relaxed' when writing to the register for the last time.
- Add trace_id ops.
- Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici…
Changes in v2:
- Modified the format of DT binging file.
- Fix compile warnings.
- Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com
---
Yuanfang Zhang (2):
dt-bindings: arm: Add device Trace Network On Chip definition
coresight: add coresight Trace Network On Chip driver
.../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++
drivers/hwtracing/coresight/Kconfig | 12 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++
4 files changed, 368 insertions(+)
---
base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164
change-id: 20250403-trace-noc-f8286b30408e
Best regards,
--
Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
This series refactors the way CPU IDs are retrieved from the device
tree.
Usually, there is a for loop that goes over every single CPU that can be
avoided. This also reduces the amount of NULL pointer checks in drivers.
I have abstracted away that loop and introduced a new function
(of_cpu_node_to_id) for this.
This patchset is a subset of [1], where I removed content and patches
relevant to hyper-threaded cores for DT. Based on the discussion, the
code refactor is still useful, hence this patchset.
Changes since v1 [2]:
- Rebased on top of the latest mainline.
- Addressed Krzysztof Kozlowski's comments -- Hopefully :-)
- Addressed Jonathan Cameron's comments.
[1] https://lore.kernel.org/all/20250512080715.82-1-alireza.sanaee@huawei.com/
[2] https://lore.kernel.org/all/20250707150414.620-1-alireza.sanaee@huawei.com/
Alireza Sanaee (5):
of: add infra for finding CPU id from phandle
arch_topology: update CPU map to use the new API
coresight: cti: Use of_cpu_phandle_to_id for grabbing CPU id
coresight: Use of_cpu_phandle_to_id for grabbing CPU id
perf/arm-dsu: refactor cpu id retrieval via new API
of_cpu_phandle_to_id
drivers/base/arch_topology.c | 16 ++++----
.../coresight/coresight-cti-platform.c | 14 +------
.../hwtracing/coresight/coresight-platform.c | 15 +------
drivers/of/cpu.c | 40 +++++++++++++++++++
drivers/perf/arm_dsu_pmu.c | 8 +---
include/linux/of.h | 9 +++++
6 files changed, 61 insertions(+), 41 deletions(-)
--
2.43.0
The Trace Network On Chip (TNOC) is an integration hierarchy which is a
hardware component that integrates the functionalities of TPDA and
funnels. It collects trace from subsystems and transfers it to coresight
sink.
In addition to the generic TNOC mentioned above, there is also a special type
of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect
TNOC doesn't need ATID. Its primary function is to connect the source of
subsystems to the Aggregator TNOC. Its driver is different from this patch and
will describe it and upstream its driver separately.
Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
---
Changes in v10:
- Rebase to coresight/next branch.
- Link to v9: https://lore.kernel.org/r/20250611-trace-noc-v9-0-4322d4cf8f4b@quicinc.com
Changes in v9:
- Mention the binding is only for Aggregator TNOC.
- Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com
Changes in v8:
- Add sysfs node to expose atid.
- Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com
Changes in v7:
- Move the content in header file into coresight-tnoc.c.
- Use scoped_guard() to replace spin_lock().
- Invoke coresight_trace_id_put_system_id() for registration failure.
- Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com
Changes in v6:
- Add a newline after return statements.
- Use 'x &= foo' to replace 'x = x & foo'.
- Use 'x |= foo' to replace 'x = x | foo'.
- Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com
Changes in v5:
- update cover-letter to describe the Interconnect TNOC.
- Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com
Changes in v4:
- Fix dt_binding warning.
- update mask of trace_noc amba_id.
- Modify driver comments.
- rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL.
- Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com
Changes in v3:
- Remove unnecessary sysfs nodes.
- update commit messages.
- Use 'writel' instead of 'write_relaxed' when writing to the register for the last time.
- Add trace_id ops.
- Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici…
Changes in v2:
- Modified the format of DT binging file.
- Fix compile warnings.
- Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com
---
Yuanfang Zhang (2):
dt-bindings: arm: Add device Trace Network On Chip definition
coresight: add coresight Trace Network On Chip driver
.../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++
drivers/hwtracing/coresight/Kconfig | 12 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++
4 files changed, 368 insertions(+)
---
base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164
change-id: 20250403-trace-noc-f8286b30408e
Best regards,
--
Yuanfang Zhang <quic_yuanfang(a)quicinc.com>
The system on chip (SoC) consists of main APSS(Applications processor
subsytem) and additional processors like modem, lpass. There is
coresight-etm driver for etm trace of APSS. Coresight remote etm driver
is for enabling and disabling the etm trace of remote processors.
It uses QMI interface to communicate with remote processors' software
and uses coresight framework to configure the connection from remote
etm source to TMC sinks.
Example to capture the remote etm trace:
Enable source:
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/remote_etm0/enable_source
Capture the trace:
cat /dev/tmc_etf0 > /data/remote_etm.bin
Disable source:
echo 0 > /sys/bus/coresight/devices/remote_etm0/enable_source
Changes since V5:
1. Fix the warning and error when compile.
2. Add traceid for remote etm.
3. Change qcom,qmi-id tp qcom,qmi-instance-id.
Changes since V4:
1. Add coresight QMI driver
2. Add coresight qmi node and qcom,qmi-id of modem-etm in msm8996 dtsi
V5: https://lwn.net/ml/all/20250424115854.2328190-1-quic_jinlmao@quicinc.com/
Changes since V3:
1. Use different compatible for different remote etms in dt.
2. Get qmi instance id from the match table data in driver.
Change since V2:
1. Change qcom,inst-id to qcom,qmi-id
2. Fix the error in code for type of remote_etm_remove
3. Depend on QMI helper in Kconfig
Changes since V1:
1. Remove unused content
2. Use CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS as remote etm source type.
3. Use enabled instead of enable in driver data.
4. Validate instance id value where it's read from the DT.
Mao Jinlong (5):
dt-bindings: arm: Add CoreSight QMI component description
coresight: Add coresight QMI driver
dt-bindings: arm: Add qcom,qmi-id for remote etm
coresight: Add remote etm support
arm64: dts: qcom: msm8996: Add coresight qmi node
.../bindings/arm/qcom,coresight-qmi.yaml | 65 +++++
.../arm/qcom,coresight-remote-etm.yaml | 9 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +
drivers/hwtracing/coresight/Kconfig | 23 ++
drivers/hwtracing/coresight/Makefile | 2 +
drivers/hwtracing/coresight/coresight-qmi.c | 198 +++++++++++++
drivers/hwtracing/coresight/coresight-qmi.h | 101 +++++++
.../coresight/coresight-remote-etm.c | 262 ++++++++++++++++++
8 files changed, 671 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-qmi.yaml
create mode 100644 drivers/hwtracing/coresight/coresight-qmi.c
create mode 100644 drivers/hwtracing/coresight/coresight-qmi.h
create mode 100644 drivers/hwtracing/coresight/coresight-remote-etm.c
--
2.25.1
The system on chip (SoC) consists of main APSS(Applications processor
subsytem) and additional processors like modem, lpass. There is
coresight-etm driver for etm trace of APSS. Coresight remote etm driver
is for enabling and disabling the etm trace of remote processors.
It uses QMI interface to communicate with remote processors' software
and uses coresight framework to configure the connection from remote
etm source to TMC sinks.
Example to capture the remote etm trace:
Enable source:
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/remote_etm0/enable_source
Capture the trace:
cat /dev/tmc_etf0 > /data/remote_etm.bin
Disable source:
echo 0 > /sys/bus/coresight/devices/remote_etm0/enable_source
Changes since V4:
1. Add coresight QMI driver
2. Add coresight qmi node and qcom,qmi-id of modem-etm in msm8996 dtsi
Changes since V3:
1. Use different compatible for different remote etms in dt.
2. Get qmi instance id from the match table data in driver.
Change since V2:
1. Change qcom,inst-id to qcom,qmi-id
2. Fix the error in code for type of remote_etm_remove
3. Depend on QMI helper in Kconfig
Changes since V1:
1. Remove unused content
2. Use CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS as remote etm source type.
3. Use enabled instead of enable in driver data.
4. Validate instance id value where it's read from the DT.
Mao Jinlong (5):
dt-bindings: arm: Add CoreSight QMI component description
coresight: Add coresight QMI driver
dt-bindings: arm: Add qcom,qmi-id for remote etm
coresight: Add remote etm support
arm64: dts: qcom: msm8996: Add coresight qmi node
.../bindings/arm/qcom,coresight-qmi.yaml | 65 +++++
.../arm/qcom,coresight-remote-etm.yaml | 10 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +
drivers/hwtracing/coresight/Kconfig | 24 ++
drivers/hwtracing/coresight/Makefile | 2 +
drivers/hwtracing/coresight/coresight-qmi.c | 209 +++++++++++++++
drivers/hwtracing/coresight/coresight-qmi.h | 107 ++++++++
.../coresight/coresight-remote-etm.c | 252 ++++++++++++++++++
8 files changed, 680 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-qmi.yaml
create mode 100644 drivers/hwtracing/coresight/coresight-qmi.c
create mode 100644 drivers/hwtracing/coresight/coresight-qmi.h
create mode 100644 drivers/hwtracing/coresight/coresight-remote-etm.c
--
2.25.1