Do some cleanups then add a new format attribute to set the timestamp
interval for ETMv4 in Perf mode. The current interval is too high for
most use cases, and particularly on the FVP the number of timestamps
generated is excessive.
Although it would be good to make only SYNC timestamps the default and
have counter timestamps opt-in, this would be a breaking change. We
can always do that later, or disable counter timestamps from Perf.
This is added as an event format attribute, rather than a Coresight
config because it's something that the driver is already configuring
automatically in Perf mode with any unused counter, so it's not possible
to modify this with a config.
Applies to coresight/next
Signed-off-by: James Clark <james.clark(a)linaro.org>
---
James Clark (6):
coresight: Change syncfreq to be a u8
coresight: Fix holes in struct etmv4_config
coresight: Repack struct etmv4_drvdata
coresight: Refactor etm4_config_timestamp_event()
coresight: Add format attribute for setting the timestamp interval
coresight: docs: Document etm4x ts_interval
Documentation/trace/coresight/coresight.rst | 14 +++
drivers/hwtracing/coresight/coresight-etm-perf.c | 6 +-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 110 +++++++++++++--------
drivers/hwtracing/coresight/coresight-etm4x.h | 86 ++++++++++------
4 files changed, 144 insertions(+), 72 deletions(-)
---
base-commit: a80198ba650f50d266d7fc4a6c5262df9970f9f2
change-id: 20250724-james-cs-syncfreq-7c2257a38ed3
Best regards,
--
James Clark <james.clark(a)linaro.org>
Do some cleanups then add a new format attribute to set the timestamp
interval for ETMv4 in Perf mode. The current interval is too high for
most use cases, and particularly on the FVP the number of timestamps
generated is excessive.
Although it would be good to make only SYNC timestamps the default and
have counter timestamps opt-in, this would be a breaking change. We
can always do that later, or disable counter timestamps from Perf.
This is added as an event format attribute, rather than a Coresight
config because it's something that the driver is already configuring
automatically in Perf mode with any unused counter, so it's not possible
to modify this with a config.
Applies to coresight/next
Signed-off-by: James Clark <james.clark(a)linaro.org>
---
Changes in v2:
- Only show the attribute for ETMv4 to improve usability and fix the
arm32 build error. Wrapping everything in
IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) isn't ideal, but the -perf.c
file is shared between ETMv3 and ETMv4, and there is already precedent
for doing it this way.
- Link to v1: https://lore.kernel.org/r/20250811-james-cs-syncfreq-v1-0-b001cd6e3404@lina…
---
James Clark (6):
coresight: Change syncfreq to be a u8
coresight: Fix holes in struct etmv4_config
coresight: Repack struct etmv4_drvdata
coresight: Refactor etm4_config_timestamp_event()
coresight: Add format attribute for setting the timestamp interval
coresight: docs: Document etm4x ts_interval
Documentation/trace/coresight/coresight.rst | 14 +++
drivers/hwtracing/coresight/coresight-etm-perf.c | 13 ++-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 110 +++++++++++++--------
drivers/hwtracing/coresight/coresight-etm4x.h | 86 ++++++++++------
4 files changed, 151 insertions(+), 72 deletions(-)
---
base-commit: a80198ba650f50d266d7fc4a6c5262df9970f9f2
change-id: 20250724-james-cs-syncfreq-7c2257a38ed3
Best regards,
--
James Clark <james.clark(a)linaro.org>
Change since V10:
1. Update kernel version to 6.18
V10 link: https://lkml.org/lkml/2025/8/6/520
Change since V9:
1. Replace scnprintf with sysfs_emit.
2. Update date in ABI files.
V9 link: https://lkml.org/lkml/2025/7/17/832
Change since V8:
1. Add label in all documentations of coresight components.
2. Add control of the visibility of the label sysfs attribute.
V8 link: https://lkml.org/lkml/2025/7/3/985
Change since V7:
1. Update the conflict when apply to coresight next.
2. Update the Date and version in ABI file.
V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.…
Change since V6:
1. Update the date and version in ABI file.
Change since V5:
1. Update the kernel version of ABI files.
2. Add link of different patch versions.
V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319…
Change since V4:
1. Add label in DT and add label sysfs node for each coresight device.
V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268…
Change since V3:
1. Change device-name to arm,cs-dev-name.
2. Add arm,cs-dev-name to only CTI and sources' dt-binding.
V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628…
Change since V2:
1. Fix the error in coresight core.
drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers
2. Fix the warning when run dtbinding check.
Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition
V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265…
Change since V1:
1. Change coresight-name to device name.
2. Add the device-name in coresight dt bindings.
V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.…
Mao Jinlong (2):
dt-bindings: arm: Add label in the coresight components
coresight: Add label sysfs node support
.../testing/sysfs-bus-coresight-devices-cti | 6 ++
.../sysfs-bus-coresight-devices-dummy-source | 6 ++
.../testing/sysfs-bus-coresight-devices-etb10 | 6 ++
.../testing/sysfs-bus-coresight-devices-etm3x | 6 ++
.../testing/sysfs-bus-coresight-devices-etm4x | 6 ++
.../sysfs-bus-coresight-devices-funnel | 6 ++
.../testing/sysfs-bus-coresight-devices-stm | 6 ++
.../testing/sysfs-bus-coresight-devices-tmc | 6 ++
.../testing/sysfs-bus-coresight-devices-tpdm | 6 ++
.../testing/sysfs-bus-coresight-devices-trbe | 6 ++
.../bindings/arm/arm,coresight-cti.yaml | 4 ++
.../arm/arm,coresight-dummy-sink.yaml | 4 ++
.../arm/arm,coresight-dummy-source.yaml | 4 ++
.../arm/arm,coresight-dynamic-funnel.yaml | 4 ++
.../arm/arm,coresight-dynamic-replicator.yaml | 4 ++
.../bindings/arm/arm,coresight-etb10.yaml | 4 ++
.../bindings/arm/arm,coresight-etm.yaml | 4 ++
.../arm/arm,coresight-static-funnel.yaml | 4 ++
.../arm/arm,coresight-static-replicator.yaml | 4 ++
.../bindings/arm/arm,coresight-tmc.yaml | 4 ++
.../bindings/arm/arm,coresight-tpiu.yaml | 4 ++
.../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++
.../arm/qcom,coresight-remote-etm.yaml | 4 ++
.../bindings/arm/qcom,coresight-tpda.yaml | 4 ++
.../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++
drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++-
26 files changed, 189 insertions(+), 2 deletions(-)
--
2.34.1
This series is to fix device registration and unregistration.
The first patch addresses the resource is not released properly for a
failure case during a device registration.
The second patch is to use mutex to protect unregistration flow.
The last three patches are for refactoring. Patch 03 explicitly uses
the parent device handler. Patch 04 separates the success and failure
flows for code readable and easier maintenance. Patch 05 improves the
error handling by invoking specific functions for resource cleanup.
Leo Yan (5):
coresight: Correct sink ID map allocation failure handling
coresight: Protect unregistration with mutex
coresight: Explicitly use the parent device handler
coresight: Separate failure and success flows
coresight: Refine error handling for device registration
drivers/hwtracing/coresight/coresight-core.c | 67 +++++++++++---------
1 file changed, 37 insertions(+), 30 deletions(-)
--
2.34.1
This patchset builds upon Yicong's previous patches [1].
Introducing fix two race issues found by using TMC-ETR and CATU, Two
cleanups found when debugging the issues.
[1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@…
---
Changes in v3:
- Patches 1: Additional comment for tmc_drvdata::etr_mode. Update
comment for tmc_drvdata::reading with Jonathan's Tag.
- Patches 2: Replace scoped_guard with guard with Jonathan's Tag.
- Patches 2: Fix spinlock to raw_spinlock, and refactor this code based
on Leo's suggested solution.
- Patches 3: change the size's type to ssize_t and use max_t to simplify
the code with Leo's Tag.
Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@…
Changes in v2:
- Updated the commit of patch2.
- Rebase to v6.16-rc1
Junhao He (1):
coresight: tmc: refactor the tmc-etr mode setting to avoid race
conditions
Yicong Yang (2):
coresight: tmc: Add missing doc including reading and etr_mode of
struct tmc_drvdata
coresight: tmc: Decouple the perf buffer allocation from sysfs mode
.../hwtracing/coresight/coresight-tmc-etr.c | 110 ++++++++----------
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
2 files changed, 53 insertions(+), 59 deletions(-)
--
2.33.0
This series fixes and improves clock usage in the Arm CoreSight drivers.
Based on the DT binding documents, the trace clock (atclk) is defined in
some CoreSight modules, but support is absent. In most cases, the issue
is hidden because the atclk clock is shared by multiple CoreSight
modules and the clock is enabled anyway by other drivers. The first
three patches address this issue.
The programming clock (pclk) management in CoreSight drivers does not
use the devm_XXX() variant APIs, the drivers needs to manually disable
and release clocks for errors and for normal module exit. However, the
drivers miss to disable clocks during module exit. The atclk may also
not be disabled in CoreSight drivers during module exit. By using devm
APIs, patches 04 and 05 fix clock disabling issues.
Another issue is pclk might be enabled twice in init phase - once by
AMBA bus driver, and again by CoreSight drivers. This is fixed in
patch 06.
Patches 07 to 10 refactor the clock related code. Patch 07 consolidates
the clock initialization into a central place. Patch 08 polishes driver
data allocation. Patch 09 makes the clock enabling sequence consistent.
Patch 09 removes redundant condition checks and adds error handling in
runtime PM.
This series has been verified on Arm64 Juno platform, for both DT and
ACPI modes.
Also tested on Hikey960 for emulating static funnel and replicator
without clock nodes. Mark kindly tested on imx8mp board.
---
Changes in v6:
- Changed to devm_clk_get_optional_enabled() for pclk, for fixing the
clock initialization failure reported by Mark.
- Added James test tags as no change for ACPI.
- Link to v5: https://lore.kernel.org/r/20250724-arm_cs_fix_clock_v4-v5-0-63f648dae021@ar…
Changes in v5:
- Skip clock management for ACPI devices (Suzuki).
- Link to v4: https://lore.kernel.org/r/20250627-arm_cs_fix_clock_v4-v4-0-0ce0009c38f8@ar…
Changes in v4:
- Separated patch 07 into two patches, one is for clock consolidation
and another is for polishing driver data allocation (Anshuman).
Changes in v3:
- Updated subjects for patches 04 and 05 (Anshuman).
- Refined condition checking "if (dev_is_amba(dev))" in patch 07
(Anshuman).
---
Leo Yan (10):
coresight: tmc: Support atclk
coresight: catu: Support atclk
coresight: etm4x: Support atclk
coresight: Appropriately disable programming clocks
coresight: Appropriately disable trace bus clocks
coresight: Avoid enable programming clock duplicately
coresight: Consolidate clock enabling
coresight: Refactor driver data allocation
coresight: Make clock sequence consistent
coresight: Refactor runtime PM
drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++---------
drivers/hwtracing/coresight/coresight-catu.h | 1 +
drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++
drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++---------
drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++-----
drivers/hwtracing/coresight/coresight-etb10.c | 18 ++----
drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++----
drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++-----
drivers/hwtracing/coresight/coresight-etm4x.h | 4 +-
drivers/hwtracing/coresight/coresight-funnel.c | 66 ++++++++--------------
drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++-------------
drivers/hwtracing/coresight/coresight-stm.c | 34 +++++------
drivers/hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++--------
drivers/hwtracing/coresight/coresight-tmc.h | 2 +
drivers/hwtracing/coresight/coresight-tpiu.c | 36 +++++-------
include/linux/coresight.h | 31 +---------
16 files changed, 228 insertions(+), 290 deletions(-)
---
base-commit: a80198ba650f50d266d7fc4a6c5262df9970f9f2
change-id: 20250627-arm_cs_fix_clock_v4-e24b1e1f8920
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
This series addresses CPU power management issues in the CoreSight
drivers. For easier review, the patches are organized into two
categories:
o Patches 01 ~ 10 focus on CPU power management within the ETM drivers.
These patches fix SMP-safe access to the mode, correct context
synchronization, and refactor the CPU suspend/resume flows.
o Patches 11 ~ 28 extend CPU power management to cover activated paths,
including helpers, links, and sinks. These changes move CPU PM and
hotplug notifiers from the ETMv4 driver into the CoreSight core layer.
Summary of Changes:
- Patches 01 ~ 03: Fix device mode access in the SMP mode.
- Patch 04 : A minor fix for polling bit.
- Patches 05 ~ 07: Improve the context synchronization based on the ETM
specification (IHI0064H.b) and Arm ARM (ARM DDI 0487
L.a).
- Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4
driver, in the end, the CPU PM callbacks reuse the
normal enabling and disabling flows.
- Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer.
- Patches 18 ~ 25: Enhance device mode handling in the CTI driver,
distinguishes debug mode from trace modes (Perf or
SysFS mode). Extend support activated paths during
CPU idle. Support save and restore context for
per-CPU sink (TRBE).
- Patches 26 ~ 28: Move CPU hotplug notifier from the ETMv4 driver to
the core layer. The full path is now managed in CPU
hotplug.
Verification:
This series has been verified on the following platforms:
- Hikey960, Juno-r0 and Juno-r2:
Note that the firmware on Hikey960 and Juno-r0 is unstable. While no
CoreSight failures were observed, but the CPU hotplug or CPU idle
itself may fail intermittently.
Juno-r2 is much stable and can pass 24+ hours stress test.
- FVP RevC: Verified TRBE changes.
Stress test script:
#!/usr/bin/bash
echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
while true; do
echo 0 > /sys/devices/system/cpu/cpu2/online;
echo 1 > /sys/devices/system/cpu/cpu2/online;
done &
while true; do
echo 1 > /sys/bus/coresight/devices/etm2/enable_source;
echo 0 > /sys/bus/coresight/devices/etm2/enable_source;
done &
---
Changes in v2:
- Refactored ETMv4 suspend and resume for reusing the normal enabling
and disabling flows (James).
- Used a per-CPU structure to maintain path pointers (James).
- Supported helpers in CPU PM flows (James).
- Fixed the SMP-safe access to device mode.
- Fixed the context synchronization in ETMv4x driver.
- Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a…
Signed-off-by: Leo Yan <leo.yan(a)arm.com>
---
Leo Yan (27):
coresight: Change device mode to atomic type
coresight: etm4x: Always set tracer's device mode on target CPU
coresight: etm3x: Always set tracer's device mode on target CPU
coresight: etm4x: Correct polling IDLE bit
coresight: etm4x: Ensure context synchronization is not ignored
coresight: etm4x: Add context synchronization before enabling trace
coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF
coresight: etm4x: Remove the state_needs_restore flag
coresight: etm4x: Add flag to control single-shot restart
coresight: etm4x: Reuse normal enable and disable logic in CPU idle
coresight: Populate CPU ID into the coresight_device structure
coresight: sysfs: Validate CPU online status for per-CPU sources
coresight: Set per CPU source pointer
coresight: Register CPU PM notifier in core layer
coresight: etm4x: Hook CPU PM callbacks
coresight: Add callback to determine if context save/restore is needed
coresight: etm4x: Remove redundant condition checks in save and restore
coresight: cti: Fix race condition by using device mode
coresight: cti: Introduce CS_MODE_DEBUG mode
coresight: cti: Properly handle modes in CPU PM notifiers
coresight: Add per-CPU path pointer
coresight: Add 'in_idle' argument to path enable/disable functions
coresight: Control path during CPU idle
coresight: Add PM callbacks for percpu sink
coresight: Take hotplug lock in enable_source_store() for Sysfs mode
coresight: Move CPU hotplug callbacks to core layer
coresight: Manage activated path during CPU hotplug
Yabin Cui (1):
coresight: trbe: Save and restore state across CPU low power state
drivers/hwtracing/coresight/coresight-catu.c | 1 +
drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++--
drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 +
drivers/hwtracing/coresight/coresight-cti-core.c | 40 +-
drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-dummy.c | 1 +
drivers/hwtracing/coresight/coresight-etb10.c | 1 +
drivers/hwtracing/coresight/coresight-etm3x-core.c | 61 ++-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 488 ++++++---------------
drivers/hwtracing/coresight/coresight-etm4x.h | 62 ---
drivers/hwtracing/coresight/coresight-funnel.c | 1 +
drivers/hwtracing/coresight/coresight-replicator.c | 1 +
drivers/hwtracing/coresight/coresight-stm.c | 1 +
drivers/hwtracing/coresight/coresight-sysfs.c | 10 +
drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
drivers/hwtracing/coresight/coresight-tpda.c | 1 +
drivers/hwtracing/coresight/coresight-tpdm.c | 1 +
drivers/hwtracing/coresight/coresight-tpiu.c | 1 +
drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++
drivers/hwtracing/coresight/ultrasoc-smb.c | 1 +
include/linux/coresight.h | 55 ++-
21 files changed, 665 insertions(+), 487 deletions(-)
---
base-commit: 66701750d5565c574af42bef0b789ce0203e3071
change-id: 20250611-arm_cs_pm_fix_v3-f4ae29bb7d81
Best regards,
--
Leo Yan <leo.yan(a)arm.com>
This patch series adds support for the Qualcomm CoreSight Interconnect TNOC
(Trace Network On Chip) block, which acts as a CoreSight graph link forwarding
trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC,
this block does not support aggregation or ATID assignment.
Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>
---
Changes in v3:
- Add detail for changes in V2.
- Remove '#address-cells' and '#size-cells' properties from in-ports field.
- Fix comment indentation for packet description.
- Link to v2: https://lore.kernel.org/r/20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com
Changes in v2:
- Removed the trailing '|' after the description in qcom,coresight-itnoc.yaml.
- Dropped the 'select' section from the YAML file.
- Updated node name to use a more generic naming convention.
- Removed the 'items' property from the compatible field.
- Deleted the description for the reg property.
- Dropped clock-names and adjusted the order of clock-names and clocks.
- Moved additionalProperties to follow the $ref of out-ports.
- Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device.
- Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com
---
Yuanfang Zhang (3):
dt-bindings: arm: qcom: Add Coresight Interconnect TNOC
coresight-tnoc: add platform driver to support Interconnect TNOC
coresight-tnoc: Add runtime PM support for Interconnect TNOC
.../bindings/arm/qcom,coresight-itnoc.yaml | 90 +++++++++++++
drivers/hwtracing/coresight/coresight-tnoc.c | 139 +++++++++++++++++++--
2 files changed, 216 insertions(+), 13 deletions(-)
---
base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca
change-id: 20250815-itnoc-460273d1b80c
Best regards,
--
Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>
On 27/08/2025 11:55 am, Jie Gan wrote:
> Patchset 1 introduces configuration of the cross-trigger registers with
> appropriate values to enable proper generation of cross-trigger packets.
>
> Patchset 2 introduces a logic to configure the TPDA_SYNCR register,
> which determines the frequency of ASYNC packet generation. These packets
> assist userspace tools in accurately identifying each valid packet.
>
> Patchset 3 introduces a sysfs node to initiate a flush request for the
> specific port, forcing the data to synchronize and be transmitted to the
> sink device.
>
> Changes in V3:
> 1. Optimizing codes according to James's comment.
> Link to V2 - https://lore.kernel.org/all/20250827042042.6786-1-jie.gan@oss.qualcomm.com/
>
> Changes in V2:
> 1. Refactoring the code based on James's comment for optimization.
> Link to V1 - https://lore.kernel.org/all/20250826070150.5603-1-jie.gan@oss.qualcomm.com/
>
> Tao Zhang (3):
> coresight: tpda: add sysfs nodes for tpda cross-trigger configuration
> coresight: tpda: add logic to configure TPDA_SYNCR register
> coresight: tpda: add sysfs node to flush specific port
>
> .../testing/sysfs-bus-coresight-devices-tpda | 50 ++++
> drivers/hwtracing/coresight/coresight-tpda.c | 278 ++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpda.h | 33 ++-
> 3 files changed, 360 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda
>
Reviewed-by: James Clark <james.clark(a)linaro.org>