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5 years, 2 months

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5 years, 2 months

Re: Secure World Coresight Tracing - HiKey 960

by Mike Leach

Hi Daniel, The CoreSight mailing list is the best place to ask these questions - I've added it to the to: section of this mail. On Fri, 19 Feb 2021 at 13:43, Daniel Su <daniel.sun.su(a)gmail.com> wrote: > > Sorry I made a mistake, I need to switch those bits but those aren't in the ETM mode sysFS parameter. > > > On Feb 19, 2021, at 14:21, Daniel Su <daniel.sun.su(a)gmail.com> wrote: > > > > Thanks, > > > > To just give a bit of background I am doing an internship to improve tracing and debugging for secure world applications in TrustZone. Originally the idea was to come up with a software solution but I thought using the hardware tracing features might be very powerful as the secure world trusted execution environments typically have less debugging and tracing functionalities built into the trusted operating system. > > > > I have been doing further reading and I believe I need to configure the ETM mode sysFS parameter. > > > > To switch these bits: > > > > /* secure state access levels - TRCACATRn */ > > #define ETM_EXLEVEL_S_APP BIT(8) > > #define ETM_EXLEVEL_S_OS BIT(9) > > #define ETM_EXLEVEL_S_HYP BIT(10) > > #define ETM_EXLEVEL_S_MON BIT(11) > > /* non-secure state access levels - TRCACATRn */ > > #define ETM_EXLEVEL_NS_APP BIT(12) > > #define ETM_EXLEVEL_NS_OS BIT(13) > > #define ETM_EXLEVEL_NS_HYP BIT(14) > > #define ETM_EXLEVEL_NS_NA BIT(15) > > ns_exlevel_vinst and s_exlevel_vinst control these bits in the TRCVICTLR. addr_exlevel_s_ns sets both S and NS bits in the TRCACATRn register currently addressed by addr_idx. In the kernel tree - Documentation/trace/coresight/coresight-etm4x-reference.rst - has lots of information on programming these sysfs files. I would advise setting mode first - which will set up some default values for TRCVITLR, then make any further adjustments you want. > > Right now I am able to capture the traces and read them out thanks to Leo Yan's command examples and presentation. > > > > I still need to figure out how to only trace branching instructions, and also how to best decode the traces. Right now even though I can read out /dev/ec036000.etf , I am unsure how to best go about interpreting the raw trace data. > > Hardware trace will trace everything - subject to certain filters - such as address filtering, exception filtering etc. It is not possible to trace only branch instructions. You will need to capture trace, decode then run an analysis on that decode to determine what branches have been taken. ETMv4 is program flow trace - so all branches are marked as taken or not taken. Consider the program:- =============== 0x1000 start: < some code > ... 0x1100 B func1 0x1200 func1: <some code> .... 0x1240 mov r0, &func2 B r0 0x2000 func2: <some code> ================ This will result in trace as follows:- TRACE_ON ADDR(0x1000) ATOM(E) > > I believe ptm2human and OpenCSD are two open source libraries that allow for decoding of the ETMv4 trace data. I understand there are paid solutions as well such as the DS-5 and Trace32 from Lauterbach to decode. > > > > Do you have any recommendations on other decoders or any tips in general as to how to decode the raw trace data into human readable format? > > > > Best, > > Daniel > > > >> On Feb 18, 2021, at 18:38, Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: > >> > >> Hi Daniel > >> > >> On 2/18/21 4:12 PM, Daniel Su wrote: > >>> Hello, > >>> First of all I want to say thanks for your work on the Coresight support as well as the presentation slides. Currently I am working with the Hikey960 which I see is supported and has been used as a reference platform in your slides. > >>> I believe it should be possible to setup self-hosted Coresight to trace only for branch instructions in the secure world. Currently I am investigating how to set this up on the Hikey960 without access to a hardware debugger. > >>> I am wondering if any of you have done this before, if there is additional documentation, or if there are any good support groups/chats/channels to ask questions. I have some experience with Coresight mainly from reading the ARM reference manuals but it is still a lot to parse. > >> > >> I haven't done anything similar. You should be able to imitate how the > >> CoreSight drivers program the components ( ETM, Funnels, Replicator and ETR). > >> > >> For ETM, you just need to make sure you don't filter out the Secure EL1/EL2/EL0. > >> You would need to read the manuals for the components or user the kernel driver > >> as the reference. > >> > >> Cheers > >> Suzuki > >> > >>> I believe in Linux I should be using `ns_exlevel_vinst` to filter out Non-Secure instructions. Also since the Hikey960 is multicore, I guess I would need to configure the top level Coresight in order to trace all cores? Would this be the ETR then? > >>> Best, > >>> Daniel > >> > > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

5 years, 2 months

[PATCH -next] coresight: etm: perf: Make symbol 'format_attr_contextid' static

by 'Wei Yongjun

From: Wei Yongjun <weiyongjun1(a)huawei.com> The sparse tool complains as follows: drivers/hwtracing/coresight/coresight-etm-perf.c:61:25: warning: symbol 'format_attr_contextid' was not declared. Should it be static? This symbol is not used outside of coresight-etm-perf.c, so this commit marks it static. Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1(a)huawei.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 0f603b4094f2..bdbb77334329 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -58,7 +58,7 @@ static ssize_t format_attr_contextid_show(struct device *dev, return sprintf(page, "config:%d\n", pid_fmt); } -struct device_attribute format_attr_contextid = +static struct device_attribute format_attr_contextid = __ATTR(contextid, 0444, format_attr_contextid_show, NULL); static struct attribute *etm_config_formats_attr[] = {

5 years, 2 months

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5 years, 2 months

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5 years, 2 months

[PATCH v3 0/8] coresight: etm-perf: Fix pid tracing with VHE

by Leo Yan

This patch series is to support PID tracing with Virtualization Host Extensions (VHE). To be backward compatibility, and can both support PID tracing for the kernel is running at either EL1 or EL2, the two new PMU formats "contextid1" and "contextid2" are introduced, which works as switches to trace PID for EL1 kernel and EL2 kernel respectively. The existed PMU format "contextid" needs to be backward compatible for users, it's changed as an alias for "contextid1" on EL1 kernel and for "contextid2" on EL2 kernel. Therefore, even without setting "contextid" config, the perf tool can dynamically pick up the config for PID tracing, the user doesn't have to set the "contexid" config manually. This patch series can be cleanly applied on perf/core branch: commit cd07e536b020 ("Merge remote-tracking branch 'torvalds/master' into perf/core") ... and applied on the mainline kernel: commit 1e0d27fce010 ("Merge branch 'akpm' (patches from Andrew)") The patch series has been tested on Arm Juno-r2 board. Verified the kernel with EL1 and didn't find issue; after some hacking in kernel driver and tool to emulate the code paths for kernel on EL2, can see the code path is hit without failure. Changes from v2: * Split into two patches for clarification comment on perf options, one patch is for kernel change and the another one is for tools' change (Suzuki); * Simplified cs_etm__get_pid_fmt() to return ETM_OPT_CTXTID2 OR ETM_OPT_CTXTID, but not both (Suzuki); * Cached "pid_fmt" in cs_etm_decoder__set_tid() (Suzuki); * Refined documentation for more clear description for PMU format usages (Mike); * Added Suzuki's and Mike's Reviewed tags. Changes from v1: * Refactored PMU formats, added formats "contextid1"/"contextid2", and reworked format "contextid" (Suzuki/Mathieu); * Refined the comments for perf configs (Leo/Mike); * Added patch 07/07 for description PID tracing in docs; * Found the issue for bitmap for option, extracted patch 03/07 for the fixing. Changes from RFC: * Added comments to clarify cases requested (Leo); * Explain the change to generic flags for cs_etm_set_option() in the commit description; * Stored PID format in metadata and passed it to decoder (Leo); * Enhanced cs-etm for backward compatibility (Denis Nikitin). Leo Yan (4): coresight: etm-perf: Clarify comment on perf options tools headers UAPI: Update tools' copy of linux/coresight-pmu.h perf cs-etm: Add helper cs_etm__get_pid_fmt() Documentation: coresight: Add PID tracing description Suzuki K Poulose (4): coresight: etm-perf: Support PID tracing for kernel at EL2 perf cs-etm: Fix bitmap for option perf cs-etm: Support PID tracing in config perf cs-etm: Detect pid in VMID for kernel running at EL2 Documentation/trace/coresight/coresight.rst | 32 ++++++++ .../hwtracing/coresight/coresight-etm-perf.c | 32 +++++++- .../coresight/coresight-etm4x-core.c | 13 ++++ include/linux/coresight-pmu.h | 20 +++-- tools/include/linux/coresight-pmu.h | 20 +++-- tools/perf/arch/arm/util/cs-etm.c | 73 +++++++++++++++---- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 38 +++++++++- tools/perf/util/cs-etm.c | 42 +++++++++++ tools/perf/util/cs-etm.h | 1 + 9 files changed, 239 insertions(+), 32 deletions(-) -- 2.25.1

5 years, 2 months

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by Ahmed

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5 years, 2 months

Proposal request for coresight [Urgent] !!

by kimyeng.kossanak

5 years, 2 months

[PATCH] coresight: etm4x: work around clang-12+ build failure

by Arnd Bergmann

From: Arnd Bergmann <arnd(a)arndb.de> clang-12 fails to build the etm4x driver with -fsanitize=array-bounds: <instantiation>:1:7: error: expected constant expression in '.inst' directive .inst (0xd5200000|((((2) << 19) | ((1) << 16) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 7) & 0x7)) << 12) | ((((((((((0x160 + (i * 4))))) >> 2))) & 0xf)) << 8) | (((((((((((0x160 + (i * 4))))) >> 2))) >> 4) & 0x7)) << 5)))|(.L__reg_num_x8)) ^ drivers/hwtracing/coresight/coresight-etm4x-core.c:702:4: note: while in macro instantiation etm4x_relaxed_read32(csa, TRCCNTVRn(i)); ^ drivers/hwtracing/coresight/coresight-etm4x.h:403:4: note: expanded from macro 'etm4x_relaxed_read32' read_etm4x_sysreg_offset((offset), false))) ^ drivers/hwtracing/coresight/coresight-etm4x.h:383:12: note: expanded from macro 'read_etm4x_sysreg_offset' __val = read_etm4x_sysreg_const_offset((offset)); \ ^ drivers/hwtracing/coresight/coresight-etm4x.h:149:2: note: expanded from macro 'read_etm4x_sysreg_const_offset' READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) ^ drivers/hwtracing/coresight/coresight-etm4x.h:144:2: note: expanded from macro 'READ_ETM4x_REG' read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) ^ arch/arm64/include/asm/sysreg.h:1108:15: note: expanded from macro 'read_sysreg_s' asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ ^ arch/arm64/include/asm/sysreg.h:1074:2: note: expanded from macro '__mrs_s' " mrs_s " v ", " __stringify(r) "\n" \ ^ It appears that the __builin_constant_p() check in read_etm4x_sysreg_offset() falsely returns 'true' here because clang decides finds that an out-of-bounds access to config->cntr_val[] cannot happen, and then it unrolls the loop with constant register numbers. Then when actually emitting the output, it fails to figure out the value again. While this is incorrect behavior in clang, it is easy to work around by avoiding the out-of-bounds array access. Do this by limiting the loop counter to the actual dimension of the array. Link: https://github.com/ClangBuiltLinux/linux/issues/1310 Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 15016f757828..4cccf874a602 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -691,13 +691,13 @@ static void etm4_disable_hw(void *info) "timeout while waiting for PM stable Trace Status\n"); /* read the status of the single shot comparators */ - for (i = 0; i < drvdata->nr_ss_cmp; i++) { + for (i = 0; i < min_t(u32, drvdata->nr_ss_cmp, ETM_MAX_SS_CMP); i++) { config->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* read back the current counter values */ - for (i = 0; i < drvdata->nr_cntr; i++) { + for (i = 0; i < min_t(u32, drvdata->nr_cntr, ETMv4_MAX_CNTR); i++) { config->cntr_val[i] = etm4x_relaxed_read32(csa, TRCCNTVRn(i)); } -- 2.29.2

5 years, 2 months

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