CoreSight

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[PATCH v1 RESEND 0/3] Add support to configure TPDM MCMB subunit

by Mao Jinlong

Introduction of TPDM MCMB(Multi-lane Continuous Multi Bit) subunit MCMB (Multi-lane CMB) is a special form of CMB dataset type. MCMB subunit has the same number and usage of registers as CMB subunit. Just like the CMB subunit, the MCMB subunit must be configured prior to enablement. This series adds support for TPDM to configure the MCMB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports MCMB subunit. All sysfs files of CMB subunit TPDM are included in MCMB subunit TPDM. On this basis, MCMB subunit TPDM will have new sysfs files to select and enable the lane. Mao Jinlong (1): coresight-tpdm: Add MCMB dataset support Tao Zhang (2): coresight-tpdm: Add support to select lane coresight-tpdm: Add support to enable the lane for MCMB TPDM .../testing/sysfs-bus-coresight-devices-tpdm | 15 +++ drivers/hwtracing/coresight/coresight-tpda.c | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 121 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 32 ++++- 4 files changed, 164 insertions(+), 9 deletions(-) -- 2.46.0

8 months, 1 week

[PATCH v10 0/8] Coresight for Kernel panic and watchdog reset

by Linu Cherian

This patch series is rebased on coresight-next-v6.12. Changelog from v9: * Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse * Reserved buffer validity and crashdata validity has been separated to avoid interdependence * New fields added to crash metadata: version, ffcr, ffsr, mode * Version checks added for metadata validation * Special file /dev/crash_tmc_xxx would be available only when crash metadata is valid * Removed READ_CRASHDATA mode meant for special casing crashdata reads. Instead, dedicated read function added for crashdata reads from reserved buffer which is common for both ETR and ETF sinks as well. * Documentation added to Documentation/tracing/coresight/panic.rst Changelog from v8: * Added missing exit path on error in __tmc_probe. * Few whitespace fixes, checkpatch fixes. * With perf sessions honouring stop_on_flush sysfs attribute, removed redundant variable stop_on_flush_en. Changelog from v7: * Fixed breakage on perf test -vvvv "arm coresight". No issues seen with and without "resrv" buffer mode * Moved the crashdev registration into a separate function. * Removed redundant variable in tmc_etr_setup_crashdata_buf * Avoided a redundant memcpy in tmc_panic_sync_etf. * Tested kernel panic with trace session started uisng perf. Please see the title "Perf based testing" below for details. For this, stop_on_flush sysfs attribute is taken into consideration while starting perf sessions as well. Changelog from v6: * Added special device files for reading crashdata, so that read_prevboot mode flag is removed. * Added new sysfs TMC device attribute, stop_on_flush. Stop on flush trigger event is disabled by default. User need to explicitly enable this from sysfs for panic stop to work. * Address parameter for panicstop ETM configuration is chosen as kernel "panic" address by default. * Added missing tmc_wait_for_tmcready during panic handling * Few other misc code rearrangements. Changelog from v5: * Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP * Fixed a memory leak while reading data from /dev/tmc_etrx in READ_PREVBOOT mode * Tested reading trace data from crashdump kernel Changelog from v4: * Device tree binding - Description is made more explicit on the usage of reserved memory region - Mismatch in memory region names in dts binding and driver fixed - Removed "mem" suffix from the memory region names * Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata", since it contains more than register snapshot. Related variables are named accordingly. * Rename struct tmc_drvdata members resrv_buf -> crash_tbuf metadata -> crash_mdata * Size field in metadata refers to RSZ register and hence indicates the size in 32 bit words. ETR metadata follows this convention, the same has been extended to ETF metadata as well. * Added crc32 for more robust metadata and tracedata validation. * Added/modified dev_dbg messages during metadata validation * Fixed a typo in patch 5 commit description Changelog from v3: * Converted the Coresight ETM driver change to a named configuration. RFC tag has been removed with this change. * Fixed yaml issues reported by "make dt_binding_check" * Added names for reserved memory regions 0 and 1 * Added prevalidation checks for metadata processing * Fixed a regression introduced in RFC v3 - TMC Status register was getting saved wrongly * Reverted memremap attribute changes from _WB to _WC to match with the dma map attributes * Introduced reserved buffer mode specific .sync op. This fixes a possible crash when reserved buffer mode was used in normal trace capture, due to unwanted dma maintenance operations. *** SUBJECT HERE *** *** BLURB HERE *** Linu Cherian (8): dt-bindings: arm: coresight-tmc: Add "memory-region" property coresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Enable panic sync handling coresight: tmc: Add support for reading crash data coresight: tmc: Stop trace capture on FlIn coresight: config: Add preloaded configuration Documentation: coresight: Panic support .../bindings/arm/arm,coresight-tmc.yaml | 26 ++ Documentation/trace/coresight/panic.rst | 356 ++++++++++++++++++ drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 ++++ drivers/hwtracing/coresight/coresight-core.c | 42 +++ .../hwtracing/coresight/coresight-tmc-core.c | 296 ++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 124 +++++- .../hwtracing/coresight/coresight-tmc-etr.c | 231 +++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 106 ++++++ include/linux/coresight.h | 24 ++ 12 files changed, 1282 insertions(+), 12 deletions(-) create mode 100644 Documentation/trace/coresight/panic.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c -- 2.34.1

8 months, 1 week

[PATCH v4 0/4] source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V4: 1. Use "coresight_get_source(path)" in the function "coresight_disable_path_from" instead of explicitly passing the source. -- Suzuki K Poulose 2. Optimize the order of the input parameters for "_coresight_build_path". -- Suzuki K Poulose 3. Reuse the method "coresight_block_source" in "_coresight_build_path". -- Suzuki K Poulose 4. Remove the unnecessary () in "coresight_build_path". -- Suzuki K Poulose 5. Add a helper to check if a device is SOURCE. -- Suzuki K Poulose 6. Adjust the posistion of setting "still_orphan" in "coresight_build_path". -- Suzuki K Poulose Changes in V3: 1. Rename the function "coresight_source_filter" to "coresight_block_source". And refine this function. -- Suzuki K Poulose 2. Rename the parameters of the function "coresight_find_out_connection" to avoid confusion. -- Suzuki K Poulose 3. Get the source of path in "coresight_enable_path" and "coresight_disable_path". -- Suzuki K Poulose 4. Fix filter source device before skip the port in "coresight_orphan_match". -- Suzuki K Poulose 5. Make sure the device still orphan if whter is a filter source firmware node but the filter source device is null. -- Suzuki K Poulose 6. Walk through the entire coresight bus and fixup the "filter_src_dev" if the source is being removed. -- Suzuki K Poulose 7. Refine the commit description of patch#2. -- Suzuki K Poulose 8. Fix the warning reported by kernel test robot. -- kernel test robot. 9. Use the source device directly if the port has a hardcoded filter in "tpda_get_element_size". -- Suzuki K Poulose Changes in V2: 1. Change the reference for endpoint property in dt-binding. -- Krzysztof Kozlowski 2. Change the property name "filter_src" to "filter-src". -- Krzysztof Kozlowski 3. Fix the errors in running 'make dt_binding_check'. -- Rob Herring 4. Pass in the source parameter instead of path. -- Suzuki K Poulose 5. Reset the "filter_src_dev" if the "src" csdev is being removed. -- Suzuki K Poulose 6. Add a warning if the "filter_src_dev" is of not the type DEV_TYPE_SOURCE. -- Suzuki K Poulose 7. Optimize the procedure for handling all possible cases. -- Suzuki K Poulose Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (4): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add support for trace filtering by source coresight: Add a helper to check if a device is source coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 19 ++- drivers/hwtracing/coresight/coresight-core.c | 116 +++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 18 +++ drivers/hwtracing/coresight/coresight-tpda.c | 13 +- include/linux/coresight.h | 12 +- 5 files changed, 155 insertions(+), 23 deletions(-) -- 2.17.1

8 months, 2 weeks

[PATCH v2] coresight: etm4x: Fix PID tracing when perf is run in an init PID namespace

by Julien Meunier

The previous implementation limited the tracing capabilities when perf was run in the init PID namespace, making it impossible to trace applications in non-init PID namespaces. This update improves the tracing process by verifying the event owner. This allows us to determine whether the user has the necessary permissions to trace the application. Cc: stable(a)vger.kernel.org Fixes: aab473867fed ("coresight: etm4x: Don't trace PID for non-root PID namespace") Signed-off-by: Julien Meunier <julien.meunier(a)nokia.com> --- Changes in v2: * Update comments --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 66d44a404ad0..cf41c42399e1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -693,9 +693,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, config->cfg |= TRCCONFIGR_TS; } - /* Only trace contextID when runs in root PID namespace */ + /* Only trace contextID when the event owner is in root PID namespace */ if ((attr->config & BIT(ETM_OPT_CTXTID)) && - task_is_in_init_pid_ns(current)) + task_is_in_init_pid_ns(event->owner)) /* bit[6], Context ID tracing bit */ config->cfg |= TRCCONFIGR_CID; @@ -709,8 +709,8 @@ static int etm4_parse_event_config(struct coresight_device *csdev, ret = -EINVAL; goto out; } - /* Only trace virtual contextID when runs in root PID namespace */ - if (task_is_in_init_pid_ns(current)) + /* Only trace virtual contextID when the event owner is in root PID namespace */ + if (task_is_in_init_pid_ns(event->owner)) config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; } -- 2.34.1

8 months, 2 weeks

OpenCSD v1.5.5 release

by Mike Leach

Version v1.5.5 is now released. Update:- Add build support for MacOS Bugfix:- Fix object cleanup in decode tree. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

8 months, 2 weeks

Re: [PATCH v4 0/2] coresight: core: Add device name support

by Mike Leach

Hi Jinlong I was suggesting using the label property - see p44, table 4.3 of the devicetree specification. e.g. node_name@node_address { label = "text description of this device instance"; } Then use the normal of_xxxx functions to extract the string value from "label". Regards Mike On Fri, 18 Oct 2024 at 09:42, Jinlong Mao <quic_jinlmao(a)quicinc.com> wrote: > > > > On 2024/7/31 23:15, Mike Leach wrote: > > Hi, > > > > 1) As per Krzysztof comment - use the standard "label" property > > > > 2) Do not use the label string as the node name - there is no > > guarantee of uniqueness which will cause issues. Please add the label > > as a sysfs file to the standard node. > > This uses the existing standard names, allowing any scripting based on > > this to continue to work, and will not cause issues with uniqueness > > > > e.g. > > This will allow : > > > > cat cti_cpu0/label > > > > to extract the additional hardware context information that you need. > > > > Thanks > > > > Mike > > Hi Mike, > > I tried to get the label in the driver code. But I don't find any > function for it. Do you know the function to get the label of the device > tree node ? > > label: node_name@node_address > > Thanks > Jinlong Mao > > > > > > > On Wed, 3 Jul 2024 at 13:24, Mao Jinlong <quic_jinlmao(a)quicinc.com> wrote: > >> > >> With current design, the name of the non-cpu bounded coresight > >> component is the device type with the number. And with 'ls' command > >> we can get the register address of the component. But from these > >> information, we can't know what the HW or system the component belongs > >> to. Add device-name in DT to support it. > >> > >> cti_sys0 -> ../../../devices/platform/soc(a)0/138f0000.cti/cti_sys0 > >> cti_sys1 -> ../../../devices/platform/soc(a)0/13900000.cti/cti_sys1 > >> tpdm0 -> ../../../devices/platform/soc(a)0/10b0d000.tpdm/tpdm0 > >> tpdm1 -> ../../../devices/platform/soc(a)0/10c28000.tpdm/tpdm1 > >> tpdm2 -> ../../../devices/platform/soc(a)0/10c29000.tpdm/tpdm2 > >> > >> Change since V3: > >> 1. Change device-name to arm,cs-dev-name. > >> 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. > >> > >> Change since V2: > >> 1. Fix the error in coresight core. > >> drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers > >> > >> 2. Fix the warning when run dtbinding check. > >> Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition > >> > >> Change since V1: > >> 1. Change coresight-name to device name. > >> 2. Add the device-name in coresight dt bindings. > >> > >> > >> Mao Jinlong (2): > >> coresight: core: Add device name support > >> dt-bindings: arm: Add device-name in the coresight components > >> > >> .../bindings/arm/arm,coresight-catu.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-cpu-debug.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-cti.yaml | 6 +++ > >> .../arm/arm,coresight-dummy-sink.yaml | 6 +++ > >> .../arm/arm,coresight-dummy-source.yaml | 6 +++ > >> .../arm/arm,coresight-dynamic-funnel.yaml | 6 +++ > >> .../arm/arm,coresight-dynamic-replicator.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-etb10.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-etm.yaml | 6 +++ > >> .../arm/arm,coresight-static-funnel.yaml | 6 +++ > >> .../arm/arm,coresight-static-replicator.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-stm.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-tmc.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-tpiu.yaml | 6 +++ > >> .../bindings/arm/qcom,coresight-tpda.yaml | 6 +++ > >> .../bindings/arm/qcom,coresight-tpdm.yaml | 6 +++ > >> drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++--------- > >> .../hwtracing/coresight/coresight-platform.c | 31 ++++++++++++++++ > >> include/linux/coresight.h | 3 +- > >> 19 files changed, 149 insertions(+), 18 deletions(-) > >> > >> Mao Jinlong (2): > >> dt-bindings: arm: Add device-name in the coresight components > >> coresight: core: Add device name support > >> > >> .../bindings/arm/arm,coresight-cti.yaml | 6 +++ > >> .../arm/arm,coresight-dummy-source.yaml | 6 +++ > >> .../bindings/arm/arm,coresight-stm.yaml | 6 +++ > >> .../bindings/arm/qcom,coresight-tpdm.yaml | 6 +++ > >> drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++--------- > >> .../hwtracing/coresight/coresight-platform.c | 30 +++++++++++++++ > >> include/linux/coresight.h | 3 +- > >> 7 files changed, 76 insertions(+), 18 deletions(-) > >> > >> -- > >> 2.41.0 > >> > > > > > > -- > > Mike Leach > > Principal Engineer, ARM Ltd. > > Manchester Design Centre. UK > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

8 months, 2 weeks

CoreSight on Nvidia Jetson

by vincent.ernst＠web.de

Hi there, I have two Nvidia Jetson Developer Kits, one AGX Xavier and one Nano. I want to use CoreSight for self-hosted trace collection (i.e. without JTAG debug probe) on these boards. I built the kernel for CoreSight configuration, but the problem is that there are no CoreSight devices at /sys/bus/coresight/devices/. Does anyone have an idea how to fix this? Any help is highly appreciated! Best regards, Vincent

8 months, 2 weeks

[PATCH v5 0/3] coresight: Add static trace id support

by Mao Jinlong

Some HW has static trace id which cannot be changed via software programming. For this case, configure the trace id in device tree with "arm,static-trace-id = <xxx>", and call coresight_trace_id_get_static_system_id with the trace id value in device probe function. The id will be reserved for the HW all the time if the device is probed. Changes since V4: 1. Use fwnode_property_read_u32 in fwnode_property_read_u32. 2. Update date and version in sysfs-bus-coresight-devices-dummy-source Changes since V3: 1. Adda new API function int coresight_trace_id_get_system_static_id(int trace_id). 2. Use the term "static trace id" for these devices where the hardware sets a non-programmable trace ID. Changes since V2: 1. Change "trace-id" to "arm,trace-id". 2. Add trace id flag for getting preferred id or ODD id. Changes since V1: 1. Add argument to coresight_trace_id_get_system_id for preferred id instead of adding new function coresight_trace_id_reserve_system_id. 2. Add constraint to trace-id in dt-binding file. Mao Jinlong (3): dt-bindings: arm: Add arm,static-trace-id for coresight dummy source coresight: Add support to get static id for system trace sources coresight: dummy: Add static trace id support for dummy source .../sysfs-bus-coresight-devices-dummy-source | 15 +++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++ drivers/hwtracing/coresight/coresight-dummy.c | 59 +++++++++++++++++-- .../hwtracing/coresight/coresight-platform.c | 9 +++ .../hwtracing/coresight/coresight-trace-id.c | 38 ++++++++---- .../hwtracing/coresight/coresight-trace-id.h | 9 +++ include/linux/coresight.h | 1 + 7 files changed, 123 insertions(+), 14 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source -- 2.17.1

8 months, 2 weeks

Re: [PATCH 1/1] coresight: trbe: Fix return value check in arm_trbe_register_coresight_cpu()

by Anshuman Khandual

On 10/18/24 19:38, Zhen Lei wrote: > Function devm_kzalloc() returns NULL instead of ERR_PTR() when it fails. Right, devm_kzalloc() calls devm_kmalloc() with additional __GFP_ZERO which returns NULL on error. > The IS_ERR() test in the return value check should be replaced with NULL > test. > > Fixes: 39744738a67d ("coresight: trbe: Allocate platform data per device") > Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") Actually this problem is caused by the following commit which had replaced coresight_get_platform_data() with devm_kzalloc() for a dummy 'desc.pdata' allocation. Earlier IS_ERR() test for the return value, was correct for coresight_get_platform_data() which returns ERR_PTR() on error, but then it should have been changed for devm_kzalloc() into a NULL check instead. 4277f035d227 ("coresight: trbe: Add a representative coresight_platform_data for TRBE") Please add "Fixes:" tag for the above commit instead. > Signed-off-by: Zhen Lei <thunder.leizhen(a)huawei.com> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 96a32b213669940..93fe9860acf16bd 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -1266,7 +1266,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp > * into the device for that purpose. > */ > desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL); > - if (IS_ERR(desc.pdata)) > + if (!desc.pdata) > goto cpu_clear; > > desc.type = CORESIGHT_DEV_TYPE_SINK; Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com>

8 months, 2 weeks

Re: [PATCH 1/1] coresight: trbe: Fix return value check in arm_trbe_register_coresight_cpu()

by James Clark

On 18/10/2024 3:08 pm, Zhen Lei wrote: > Function devm_kzalloc() returns NULL instead of ERR_PTR() when it fails. > The IS_ERR() test in the return value check should be replaced with NULL > test. > > Fixes: 39744738a67d ("coresight: trbe: Allocate platform data per device") > Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") I don't think the code that this patches exists in 3fbf7f011f24, but it looks ok for 39744738a67d. > Signed-off-by: Zhen Lei <thunder.leizhen(a)huawei.com> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 96a32b213669940..93fe9860acf16bd 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -1266,7 +1266,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp > * into the device for that purpose. > */ > desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL); > - if (IS_ERR(desc.pdata)) > + if (!desc.pdata) > goto cpu_clear; > > desc.type = CORESIGHT_DEV_TYPE_SINK; Reviewed-by: James Clark <james.clark(a)linaro.org>

8 months, 3 weeks

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