CoreSight

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2394 discussions

Re: [PATCH 2/2] perf report: Don't add to histogram when there is no thread found

by James Clark

On 27/06/2023 18:19, Ian Rogers wrote: > On Tue, Jun 27, 2023 at 9:58 AM Namhyung Kim <namhyung(a)kernel.org> wrote: >> >> On Tue, Jun 27, 2023 at 9:43 AM Ian Rogers <irogers(a)google.com> wrote: >>> >>> On Mon, Jun 26, 2023 at 5:02 PM Namhyung Kim <namhyung(a)kernel.org> wrote: >>>> >>>> On Mon, Jun 26, 2023 at 05:10:58PM +0100, James Clark wrote: >>>>> thread__find_map() chooses to exit without assigning a thread to the >>>>> addr_location in some scenarios, for example when there are samples from >>>>> a guest and perf_guest == false. This results in a segfault when adding >>>>> to the histogram because it uses unguarded accesses to the thread member >>>>> of the addr_location. >>>> >>>> Looking at the commit 0dd5041c9a0ea ("perf addr_location: Add >>>> init/exit/copy functions") that introduced the change, I'm not sure if >>>> it's the intend behavior. >>>> >>>> It might change maps and map, but not thread. Then I think no reason >>>> to not set the al->thread at the beginning. >>>> >>>> How about this? Ian? >>>> (I guess we can get rid of the duplicate 'al->map = NULL' part) >>> >>> It seemed strange that we were failing to find a map (the function's >>> purpose) but then populating the address_location. The change below >>> brings back that somewhat odd behavior. I'm okay with reverting to the >>> old behavior, clearly there were users relying on it. We should >>> probably also copy maps and not just thread, as that was the previous >>> behavior. >> >> Probably. But it used to support samples without maps and I think >> that's why it ignores the return value of thread__find_map(). So >> we can expect al.map is NULL and maybe fine to leave it for now. >> >> As machine__resolve() returns -1 if it gets no thread, we should set >> al.thread when it returns 0. >> >> Can I get your Acked-by? > > Yep: > Acked-by: Ian Rogers <irogers(a)google.com> Looks good to me too. Should I resend the set with this change instead of my one? > > Thanks, > Ian > >> Thanks, >> Namhyung

2 years

Re: [PATCH v6 09/13] Add nodes for dsb edge control

by Tao Zhang

On 6/20/2023 4:49 PM, Greg Kroah-Hartman wrote: > On Tue, Jun 20, 2023 at 04:31:59PM +0800, Tao Zhang wrote: >> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>> Add the nodes to set value for DSB edge control and DSB edge >>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>> resgisters to configure edge control. DSB edge detection control >>>> 00: Rising edge detection >>>> 01: Falling edge detection >>>> 10: Rising and falling edge detection (toggle detection) >>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>> configure mask. Eight 32 bit registers providing DSB interface >>>> edge detection mask control. >>>> >>>> Signed-off-by: Tao Zhang<quic_taozha(a)quicinc.com> >>>> --- >>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 ++++++++++++++++++++- >>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> index 2a82cd0..34189e4a 100644 >>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> @@ -60,3 +60,35 @@ Description: >>>> Bit[3] : Set to 0 for low performance mode. >>>> Set to 1 for high performance mode. >>>> Bit[4:8] : Select byte lane for high performance mode. >>>> + >>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>> +Date: March 2023 >>>> +KernelVersion 6.5 >>>> +Contact: Jinlong Mao (QUIC)<quic_jinlmao(a)quicinc.com>, Tao Zhang (QUIC)<quic_taozha(a)quicinc.com> >>>> +Description: >>>> + Read/Write a set of the edge control registers of the DSB >>>> + in TPDM. >>>> + >>>> + Expected format is the following: >>>> + <integer1> <integer2> <integer3> >>> sysfs is "one value", not 3. Please never have to parse a sysfs file. >> Do you mean sysfs file can only accept "one value"? > Yes. Hi Greg, I‘d like to clarify the usage of this sysfs file again. In the current design, three integers will be written to "dsb_edge_ctrl" to configure DSB edge detection. Integer #1: The start number of edge detection which needs to be configured. Integer #2: The end number of edge detection which needs to be configured. Integer #3: The type of the edge detection needs to be configured. Below is an example. echo 0x3 0x25 0x1 > dsb_edge_ctrl It will configure edge detection #3 to #37 as "falling edge detection". Since these three integers are interrelated and written to achieve the same function, can we use these three integers as "one tuple" here? Best, Tao > >> I see that more than one value are written to the sysfs file >> "trigout_attach". > Then someone missed that and it needs to be fixed. > >>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>> + struct device_attribute *attr, >>>> + char *buf) >>>> +{ >>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>> + ssize_t size = 0; >>>> + unsigned long bytes; >>>> + int i; >>>> + >>>> + spin_lock(&drvdata->spinlock); >>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>> + bytes = sysfs_emit_at(buf, size, >>>> + "Index:0x%x Val:0x%x\n", i, >>> Again, no, one value, no "string" needed to parse anything. >> I also see other sysfs files can be read more than one value in other >> drivers. > Again, they are broken, please send patches to fix them. > >> Is this "one value" limitation the usage rule of Linux sysfs system? > Yes. > > thanks, > > greg k-h

2 years

Re: [PATCH V5 6/6] coresight: etm4x: Add ACPI support in platform driver

by Suzuki K Poulose

On 27/06/2023 10:20, Greg Kroah-Hartman wrote: > On Tue, Jun 27, 2023 at 10:06:11AM +0100, Suzuki K Poulose wrote: >> Hi Greg, >> >> On 29/05/2023 07:25, Anshuman Khandual wrote: >>> From: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> >>> Drop ETM4X ACPI ID from the AMBA ACPI device list, and instead just move it >>> inside the new ACPI devices list detected and used via platform driver. >>> >>> Cc: "Rafael J. Wysocki" <rafael(a)kernel.org> >>> Cc: Len Brown <lenb(a)kernel.org> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> Cc: Mike Leach <mike.leach(a)linaro.org> >>> Cc: Leo Yan <leo.yan(a)linaro.org> >>> Cc: Sudeep Holla <sudeep.holla(a)arm.com> >>> Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> >>> Cc: linux-acpi(a)vger.kernel.org >>> Cc: coresight(a)lists.linaro.org >>> Cc: linux-arm-kernel(a)lists.infradead.org >>> Cc: linux-kernel(a)vger.kernel.org >>> Reviewed-by: Sudeep Holla <sudeep.holla(a)arm.com> (for ACPI specific changes) >>> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> --- >>> drivers/acpi/acpi_amba.c | 1 - >>> drivers/hwtracing/coresight/coresight-etm4x-core.c | 10 ++++++++++ >>> 2 files changed, 10 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c >>> index f5b443ab01c2..099966cbac5a 100644 >>> --- a/drivers/acpi/acpi_amba.c >>> +++ b/drivers/acpi/acpi_amba.c >>> @@ -22,7 +22,6 @@ >>> static const struct acpi_device_id amba_id_list[] = { >>> {"ARMH0061", 0}, /* PL061 GPIO Device */ >>> {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */ >>> - {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ >>> {"ARMHC501", 0}, /* ARM CoreSight ETR */ >>> {"ARMHC502", 0}, /* ARM CoreSight STM */ >>> {"ARMHC503", 0}, /* ARM CoreSight Debug */ >> >> This is a bit awkward request. >> >> I would like to get your opinion on merging this to coresight tree. >> This change is removing the coresight ETMv4 from the ACPI AMBA >> scan list and moving it to the coresight driver. This change is >> essential for >> 1) Adding ACPI support for later versions of ETMv4 that are not AMBA >> devices. >> 2) Adding power management support for AMBA ETMv4 with ACPI. >> >> The above change has been reviewed by Sudeep (Arm64 ACPI reviewer), but >> hasn't been Acked by the ACPI maintainer (Rafael) even after a month of >> follow up with at least 4 reminders [0]. >> >> Are you happy with the Reviews from Sudeep and given the minimal >> change to the drivers/acpi/acpi_amba.c file ? > > As we can't do anything now with the merge window open, please resend > after 6.5-rc1 is out and ask for the ACPI developers to ack this. Sure, will do that. Thanks Greg

2 years

[PATCH V5 0/6] coresight: etm4x: Migrate ACPI AMBA devices to platform driver

by Anshuman Khandual

CoreSight ETM4x devices could be accessed either via MMIO (handled via amba_driver) or CPU system instructions (handled via platform driver). But this has the following issues : - Each new CPU comes up with its own PID and thus we need to keep on adding the "known" PIDs to get it working with AMBA driver. While the ETM4 architecture (and CoreSight architecture) defines way to identify a device as ETM4. Thus older kernels won't be able to "discover" a newer CPU, unless we add the PIDs. - With ACPI, the ETM4x devices have the same HID to identify the device irrespective of the mode of access. This creates a problem where two different drivers (both AMBA based driver and platform driver) would hook into the "HID" and could conflict. e.g., if AMBA driver gets hold of a non-MMIO device, the probe fails. If we have single driver hooked into the given "HID", we could handle them seamlessly, irrespective of the mode of access. - CoreSight is heavily dependent on the runtime power management. With ACPI, amba_driver doesn't get us anywhere with handling the power and thus one need to always turn the power ON to use them. Moving to platform driver gives us the power management for free. Due to all of the above, we are moving ACPI MMIO based etm4x devices to be supported via tha platform driver. The series makes the existing platform driver generic to handle both type of the access modes. Although existing AMBA driver would still continue to support DT based etm4x MMIO devices. Although some problems still remain, such as manually adding PIDs for all new AMBA DT based devices. The series applies on 6.4-rc4. Changes in V5: - Updated the comment for apb clock in drvdata structure - Updated conditional check in etm4_runtime_suspend/resume() - Asserted that the APB clock is present and also enabled Changes in V4: https://lore.kernel.org/all/20230523044553.1525048-1-anshuman.khandual@arm.… - Changed in-code comment in etm4_check_arch_features() - Re-ordered pm_runtime_disable() in etm4_remove_platform_dev() - Renamed back etm4_match as etm4_sysreg_match - Moved back [PATCH 6/6] as [PATCH 5/6] Changes in V3: https://lore.kernel.org/all/20230519052149.1367814-1-anshuman.khandual@arm.… - Returned from etm4_check_arch_features() for non iomem devices - Renamed ETM_DEVTYPE_ETMv4x_ARCH as CS_DEVTYPE_PE_TRACE - Renamed is_etm4x_devtype() as is_devtype_cpu_trace() - Added a patch to ignore the absence of graph connections Changes in V2: https://lore.kernel.org/all/20230327050537.30861-1-anshuman.khandual@arm.co… - Enables ACPI etm4x device support in the existing platform driver - Dropped last two patches from the series - Dropped redundant 'devarch' checking from is_etm4x_device() - Renamed updated is_etm4x_device() as is_etm4x_devtype() - Fixed arguments in fallback stub for etm4_check_arch_features() - Tagged etm4_dev_pm_ops with etm4_platform_driver - Updated the comment for coresight_get_enable_apb_pclk() helper - Updated the comment for new 'pclk' element in struct etm4_drvdata - Dropped the clock when devm_ioremap_resource() fails - Convert IS_ERR() into a direct pointer check in etm4_remove_platform_dev() - Dropped "arm,coresight-etm4x" compatible property from etm4_match[] Changes in V1: https://lore.kernel.org/all/20230317030501.1811905-1-anshuman.khandual@arm.… Cc: Ganapatrao Kulkarni <gankulkarni(a)os.amperecomputing.com> Cc: Steve Clevenger <scclevenger(a)os.amperecomputing.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Frank Rowand <frowand.list(a)gmail.com> Cc: Russell King (Oracle) <linux(a)armlinux.org.uk> Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael(a)kernel.org> Cc: Len Brown <lenb(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: devicetree(a)vger.kernel.org Cc: linux-acpi(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Anshuman Khandual (4): coresight: etm4x: Allocate and device assign 'struct etmv4_drvdata' earlier coresight: etm4x: Drop iomem 'base' argument from etm4_probe() coresight: etm4x: Drop pid argument from etm4_probe() coresight: etm4x: Change etm4_platform_driver driver for MMIO devices Suzuki K Poulose (2): coresight: platform: acpi: Ignore the absence of graph coresight: etm4x: Add ACPI support in platform driver drivers/acpi/acpi_amba.c | 1 - .../coresight/coresight-etm4x-core.c | 117 ++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 4 + .../hwtracing/coresight/coresight-platform.c | 6 +- include/linux/coresight.h | 59 +++++++++ 5 files changed, 163 insertions(+), 24 deletions(-) -- 2.25.1

2 years

[PATCH 0/2] perf cs-etm: Track exception level fixups

by James Clark

A couple of changes related to edge cases since commit 8d3031d39fe8 ("perf cs-etm: Track exception level"). I think the second one is low risk seeing as any path requiring a thread leading up to adding to the histogram would already have been crashing. Maybe the thread check could also be added to hist_entry_iter__add() although other users of it don't seem to have the same issue, and there is another use of al.thread above in builtin-report.c so it's probably ok where I've added it. Applies to perf-tools-next/perf-tools-next (929ff679b69) James Clark (2): perf cs-etm: Handle per-thread mode on EL1 host kernel case perf report: Don't add to histogram when there is no thread found tools/perf/builtin-report.c | 3 +++ tools/perf/util/cs-etm.c | 11 +++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) base-commit: 929ff679b694f0f9656aec38b3a7d5c440c5ca24 -- 2.34.1

2 years

[GIT PULL] coresight: updates for v6.5

by Suzuki K Poulose

Greg, Please find the changes for coresight and hwtracing subsystem, targeting v6.5. Please note that, I have pulled James' devm_krealloc_array() patch - ( commit d388f06aced3 "devres: Provide krealloc_array" ) - into the coresight tree from your driver-core-next, for CTI module refcount fixes depend on it. Please let me know if this looks alright and kindly pull if it is fine. Kind regards Suzuki The following changes since commit 7877cb91f1081754a1487c144d85dc0d2e2e7fc4: Linux 6.4-rc4 (2023-05-28 07:49:00 -0400) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.5 for you to fetch changes up to 6c50384ef8b94a527445e3694ae6549e1f15d859: hwtracing: hisi_ptt: Fix potential sleep in atomic context (2023-06-21 11:52:39 +0100) ---------------------------------------------------------------- coresight: Updates for v6.5 CoreSight and hwtracing subsystem updates for v6.5 includes: - Fixes to the CTI module reference leaks. This involves, redesign of how the helper devices are tracked and CTI devices have been converted to helper devices. - Fix removal of the trctraceidr file from sysfs for ETMs. - Match all ETMv4 instances based on the ETMv4 architected registers and the CoreSight Component ID (CID), than having to add individual PIDs for CPUs. - Add support for Dummy CoreSight source and sink drivers. - Add James Clark as Reviewer for the CoreSight kernel drivers - Fixes to HiSilicon PCIe Tune and Trace Device driver Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Hao Zhang (3): Coresight: Add coresight dummy driver dt-bindings: arm: Add support for Coresight dummy trace Documentation: trace: Add documentation for Coresight Dummy Trace James Clark (14): devres: Provide krealloc_array coresight: Fix loss of connection info when a module is unloaded coresight: Use enum type for cs_mode wherever possible coresight: Change name of pdata->conns coresight: Rename nr_outports to nr_outconns coresight: Rename connection members to make the direction explicit coresight: Dynamically add connections coresight: Store pointers to connections rather than an array of them coresight: Simplify connection fixup mechanism coresight: Store in-connections as well as out-connections coresight: Make refcount a property of the connection coresight: Refactor out buffer allocation function for ETR coresight: Enable and disable helper devices adjacent to the path coresight: Fix CTI module refcount leak by making it a helper device Mike Leach (1): coresight: etm4x: Fix missing trctraceidr file in sysfs Nathan Chancellor (1): coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable() Suzuki K Poulose (2): coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE MAINTAINERS: coresight: Add James Clark as Reviewer Uwe Kleine-König (1): coresight: etm4x: Make etm4_remove_dev() return void Yicong Yang (5): hwtracing: hisi_ptt: Factor out filter allocation and release operation hwtracing: hisi_ptt: Add support for dynamically updating the filter list hwtracing: hisi_ptt: Export available filters through sysfs hwtracing: hisi_ptt: Advertise PERF_PMU_CAP_NO_EXCLUDE for PTT PMU hwtracing: hisi_ptt: Fix potential sleep in atomic context Documentation/ABI/testing/sysfs-devices-hisi_ptt | 52 ++ .../bindings/arm/arm,coresight-dummy-sink.yaml | 73 +++ .../bindings/arm/arm,coresight-dummy-source.yaml | 71 +++ Documentation/driver-api/driver-model/devres.rst | 1 + Documentation/trace/coresight/coresight-dummy.rst | 32 ++ Documentation/trace/hisi-ptt.rst | 12 +- MAINTAINERS | 1 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-catu.c | 21 +- drivers/hwtracing/coresight/coresight-core.c | 623 +++++++++++---------- drivers/hwtracing/coresight/coresight-cti-core.c | 52 +- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 4 +- drivers/hwtracing/coresight/coresight-cti.h | 4 +- drivers/hwtracing/coresight/coresight-dummy.c | 163 ++++++ drivers/hwtracing/coresight/coresight-etb10.c | 13 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-funnel.c | 26 +- drivers/hwtracing/coresight/coresight-platform.c | 269 ++++----- drivers/hwtracing/coresight/coresight-priv.h | 36 +- drivers/hwtracing/coresight/coresight-replicator.c | 23 +- drivers/hwtracing/coresight/coresight-stm.c | 6 +- drivers/hwtracing/coresight/coresight-sysfs.c | 17 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 26 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 110 ++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpda.c | 23 +- drivers/hwtracing/coresight/coresight-tpdm.c | 4 +- drivers/hwtracing/coresight/coresight-tpiu.c | 7 +- drivers/hwtracing/coresight/coresight-trbe.c | 3 +- drivers/hwtracing/coresight/ultrasoc-smb.c | 11 +- drivers/hwtracing/coresight/ultrasoc-smb.h | 2 +- drivers/hwtracing/ptt/hisi_ptt.c | 454 +++++++++++++-- drivers/hwtracing/ptt/hisi_ptt.h | 56 ++ include/linux/coresight.h | 127 +++-- include/linux/device.h | 11 + 39 files changed, 1662 insertions(+), 742 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml create mode 100644 Documentation/trace/coresight/coresight-dummy.rst create mode 100644 drivers/hwtracing/coresight/coresight-dummy.c

2 years

[PATCH v6 00/13] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This patch series depends on patch series "[PATCH v6 0/9] coresight: Fix CTI module refcount leak by making it a helper device" https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230425143542.… TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v6 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v6 Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 169 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 96 ++- drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 721 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 83 +++ include/linux/coresight.h | 1 + 8 files changed, 1077 insertions(+), 18 deletions(-) -- 2.7.4

2 years

Re: [PATCH] coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable()

by Suzuki K Poulose

On Fri, 16 Jun 2023 09:41:30 -0700, Nathan Chancellor wrote: > Clang's kernel Control Flow Integrity (kCFI) is a compiler-based > security mitigation that ensures the target of an indirect function call > matches the expected type of the call and trapping if they do not match > exactly. The warning -Wincompatible-function-pointer-types-strict aims > to catch these issues at compile time, which reveals: > > drivers/hwtracing/coresight/coresight-dummy.c:53:12: error: incompatible function pointer types initializing 'int (*)(struct coresight_device *, struct perf_event *, enum cs_mode)' with an expression of type 'int (struct coresight_device *, struct perf_event *, u32)' (aka 'int (struct coresight_device *, struct perf_event *, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict] > 53 | .enable = dummy_source_enable, > | ^~~~~~~~~~~~~~~~~~~ > drivers/hwtracing/coresight/coresight-dummy.c:62:12: error: incompatible function pointer types initializing 'int (*)(struct coresight_device *, enum cs_mode, void *)' with an expression of type 'int (struct coresight_device *, u32, void *)' (aka 'int (struct coresight_device *, unsigned int, void *)') [-Werror,-Wincompatible-function-pointer-types-strict] > 62 | .enable = dummy_sink_enable, > | ^~~~~~~~~~~~~~~~~ > 2 errors generated. > > [...] Applied, thanks! [1/1] coresight: dummy: Update type of mode parameter in dummy_{sink,source}_enable() commit: 185891f03f712639c082e08fc9986ff214b5d617 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 years

[RFC PATCH 0/5]Extending Coresight for Kernel panic and watchdog reset

by Linu Cherian

Hi, Sharing here the design notes and work in progress patches to get some early feedback on the implementation approach. Introduction ============ This RFC is about extending Linux coresight driver support to address kernel panic and watchdog reset scenarios. This would help coresight users to debug kernel panic and watchdog reset with the help of coresight trace data. For simplicity, watchdog and kernel panic are addressed in separate sections. Coresight trace capture: Kernel panic ------------------------------------- From the coresight driver point of view, addressing the kernel panic situation has four main requirements. a. Support for allocation of trace buffer pages from reserved memory area. Platform can advertise this using a new device tree property added to relevant coresight nodes. b. Support for stopping coresight blocks at the time of panic c. Saving required metadata in the specified format d. Support for reading trace data captured at the time of panic Allocation of trace buffer pages from reserved RAM ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A new optional device tree property "memory-region" will be added to the ETR/ETF device nodes, that would give the base address and size of trace buffer. Static allocation of trace buffers would ensure that both IOMMU enabled and disabled cases are handled. Also, platforms that support persistent RAM will allow users to read trace data in the subsequent boot without booting the crashdump kernel. Note: For ETR sink devices, this reserved region will be used for both trace capture and trace data retrieval. For ETF sink devices, internal SRAM would be used for trace capture, and they would be synced to reserved region for retrieval. Disabling coresight blocks at the time of panic ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In order to avoid the situation of losing relevant trace data after a kernel panic, it would be desirable to stop the coresight blocks at the time of panic. This can be achieved by configuring the comparator, CTI and sink devices as below, Comparator(triggers on kernel panic) --->External out --->CTI -- | ETR/ETF stop <------External In <-------------- Note: No supporting patches are shared for this, since we are planning to make use of the System configuration manager to achieve the required configuration. This is a work in progress. Saving metadata at the time of kernel panic ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Coresight metadata involves all additional data that are required for a successful trace decode in addition to the trace data. This involves ETR/ETF, ETE register snapshot etc. A new optional device property "memory-region" will be added to the ETR/ETF/ETE device nodes for this. Reading trace data captured at the time of panic ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Trace data captured at the time of panic, can be read from rebooted kernel or from crashdump kernel using the below mentioned interface. Steps for reading trace data captured in previous boot ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1. cd /sys/bus/coresight/devices/tmc_etrXX/ 2. Change to special mode called, read_prevboot. #echo 1 > read_prevboot 3. Dump trace buffer data to a file, #dd if=/dev/tmc_etrXX of=~/cstrace.bin 4. Reset back to normal mode #echo 0 > read_prevboot General flow of trace capture and decode incase of kernel panic ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1. Enable source and sink on all the cores using the sysfs interface. ETR sink will have trace buffers allocated from reserved memory. 2. Run relevant tests. 3. On a kernel panic, all coresight blocks are disabled, necessary metadata is synced by kernel panic handler. System would eventually reboot or boot a crashdump kernel. 4. For platforms that supports crashdump kernel, raw trace data can be dumped using the coresight sysfs interface from the crashdump kernel itself. Persistent RAM is not a requirement in this case. 5. For platforms that supports persistent RAM, trace data can be dumped using the the coresight sysfs interface in the subsequent Linux boot. Crashdump kernel is not a requirement in this case. Persistent RAM ensures that trace data is intact across reboot. Coresight trace capture: Watchdog reset --------------------------------------- The main difference between addressing the watchdog reset and kernel panic case are below, a. Saving coresight metadata need to be taken care by the SCP(system control processor) firmware in the specified format, instead of kernel. b. Reserved memory region given by firmware for trace buffer and metadata has to be in persistent RAM. Note: This is a requirement for watchdog reset case but optional in kernel panic case. Watchdog reset can be supported only on platforms that meet the above two requirements. Testing so far: --------------- Watchdog reset has been tested on Marvell SOCs using the above approach on 5.x kernel version with sysfs method. Linu Cherian (5): dt-bindings: arm: coresight-tmc: Add "memory-region" property ccoresight: tmc-etr: Add support to use reserved trace memory coresight: core: Add provision for panic callbacks coresight: tmc: Add support for panic sync handling coresight: tmc: Add support for reading tracedata from previous boot .../bindings/arm/arm,coresight-tmc.yaml | 9 ++ drivers/hwtracing/coresight/coresight-core.c | 31 +++++ drivers/hwtracing/coresight/coresight-priv.h | 1 + .../hwtracing/coresight/coresight-tmc-core.c | 112 ++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etf.c | 69 +++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 98 ++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 32 +++++ include/linux/coresight.h | 11 ++ 8 files changed, 362 insertions(+), 1 deletion(-) -- 2.31.1

2 years

[PATCH v5 00/13] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This patch series depends on patch series "[PATCH v6 0/9] coresight: Fix CTI module refcount leak by making it a helper device" https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230425143542.… TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v5 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v5 Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 169 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 96 ++- drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 721 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 83 +++ include/linux/coresight.h | 1 + 8 files changed, 1077 insertions(+), 18 deletions(-) -- 2.7.4

2 years

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