CoreSight

coresight@lists.linaro.org

5 participants
2101 discussions

by Tony Beig

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4 years, 6 months

OpenCSD library for a Multi-Threaded application

by subhasish Karmakar

Hi, Can I use OpenCSD library in a Multi-Threaded application? I maintain decode tree handle per thread. Code Example:/********* Initialization code *********/ ------------------------------ //dcdtree_handle_ and p_context is maintained per thread dcdtree_handle_ = ocsd_create_dcd_tree(OCSD_TRC_SRC_FRAME_FORMATTED, OCSD_DFRMTR_FRAME_MEM_ALIGN); ret = ocsd_dt_create_decoder(dcdtree_handle_, p_name, OCSD_CREATE_FLG_FULL_DECODER, p_cfg, &CSID); ret = ocsd_dt_attach_packet_callback( dcdtree_handle_, CSID, OCSD_C_API_CB_PKT_MON, (void *)packetMonitorCallBack, p_context); ret = ocsd_dt_set_gen_elem_outfn( dcdtree_handle_, genTraceElemCallBack, p_context); ------------------------------ /********* Packet Processing *********/ ------------------------------ //Each thread uses below function to process incoming CoreSight packet while ((bytes_done < (uint32_t)block_size) && (ret == OCSD_OK)) { if (OCSD_DATA_RESP_IS_CONT(dp_ret)) { dp_ret = ocsd_dt_process_data( dcdtree_handle_, OCSD_OP_DATA, block_index + bytes_done, block_size - bytes_done, ((uint8_t *)p_block) + bytes_done, &bytes_this_time); //Example code from ------------------------------ Kindly respond to my query. Thank you, Subhasish

4 years, 6 months

Urgent COVID-19: PPE / Masks

by Tony FB

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4 years, 6 months

[PATCH] coresight: etm4x: Add support for Neoverse N1 ETM

by Anurag Koul

Add PID for Arm Neoverse N1 ETM to the list of supported/known ETMs. Signed-off-by: Anurag Koul <anurag.koul(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm4x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 0b2c7c7efacb..7443a2e4528d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1541,6 +1541,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ -- 2.17.1

4 years, 6 months

😷 COVID-19: Face Mask Stock

by Tony FB

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4 years, 6 months

[RFC PATCH 0/5] Allow CoreSight to specify and select default sink

by Mike Leach

This patchset provides a proposed infrastructure to allow for the automatic selection of a sink during CoreSight tracing operations. Currently starting tracing using perf requires a sink selection on the command line:- sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a After this set the infrastructure will be able to select a default sink:- sudo ./perf record -e cs_etm// --per-thread uname -a This matches with the default operation provided with perf and intelpt. The CoreSight infrastructure is updated to allow the concept of a "principal sink". For any given source there could be multiple possible sinks available for selection. However, there are no good programmatic ways to determine the optimal sink for a given topolgy. For any given rule (e.g. first sink found, first ETR, last ETR), there exists a possible platform / topology that will not be suitable. Therefore, we select the principal sink using a property in the device tree. This allows the routine to select the best possible for the situation. The only rule for selecting such sinks, is that there should only be one principal sink marked for any given source, across all possible paths from that source to any sinks. (if this rule is violated then the first found will be used) Therefore to select a sink, we start with the source, and walk the child connections until a sink marked as a principal sink is found. Applied to Linux 5.7-rc1 (with dts updates 1,2), tested on Juno / DB410 Note A: Moving forward to topologies which have groups of sources going to dedicated sinks e.g. multisocket / multicluster where each socket / cluster has a sink, then multiple sinks can be marked as principal sink, one for each cluster. The same applies to 1:1 ETM:sink topolgy were each sink will be marked. Note B: The current set does not auto-select when using sysfs, but I believe this could easily be added. [1] https://lists.linaro.org/pipermail/coresight/2020-April/003819.html [2] https://lists.linaro.org/pipermail/coresight/2020-April/003821.html Mike Leach (5): coresight: Add principal sink handling to CoreSight base coresight: tmc: Add principal sink attribute detection coresight: etm: perf: Add default sink selection to etm perf perf: cs-etm: Allow no CoreSight sink to be specified on command line dt-bindings: arm: qcom: Add CoreSight principal sink select parameters arch/arm64/boot/dts/arm/juno-base.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + .../hwtracing/coresight/coresight-etm-perf.c | 20 +++++++++-- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ drivers/hwtracing/coresight/coresight-tmc.c | 9 +++++ drivers/hwtracing/coresight/coresight.c | 34 +++++++++++++++++++ include/linux/coresight.h | 7 ++++ tools/perf/arch/arm/util/cs-etm.c | 6 ++-- 8 files changed, 74 insertions(+), 6 deletions(-) -- 2.17.1

4 years, 6 months

[PATCH] coresight: cti: Add power management to CTI driver

by Mike Leach

Add in CPU hotplug and CPU idle power management handling to CTI driver. Only CPU bound CTIs will register with the PM routines, to enable PM of CTI alongside PM of ETM devices. Need separate HP PM event CPUHP_AP_ARM_CORESIGHT_CTI_STARTING as events can only be registered once. Applies to Linux 5.7-rc1, tested on platforms Juno-r1 and DB410c. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-cti.c | 163 +++++++++++++++++++- include/linux/cpuhotplug.h | 1 + 2 files changed, 156 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index aa6e0249bd70..31996a20ce69 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -5,6 +5,7 @@ */ #include <linux/property.h> +#include <linux/cpu_pm.h> #include "coresight-cti.h" /** @@ -27,6 +28,12 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) +/* power management handling */ +static int nr_cti_cpu; + +/* quick lookup list for CPU bound CTIs when power handling */ +static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; + /* * CTI naming. CTI bound to cores will have the name cti_cpu<N> where * N is the CPU ID. System CTIs will have the name cti_sys<I> where I @@ -36,7 +43,7 @@ static DEFINE_MUTEX(ect_mutex); */ DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); -/* write set of regs to hardware - call with spinlock claimed */ +/* write set of regs to hardware - call with spinlock claimed / cpu context */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; @@ -73,7 +80,7 @@ static void cti_enable_hw_smp_call(void *info) } /* write regs to hardware and enable */ -static int cti_enable_hw(struct cti_drvdata *drvdata) +static int cti_enable_hw(struct cti_drvdata *drvdata, bool hp_re_enable) { struct cti_config *config = &drvdata->config; struct device *dev = &drvdata->csdev->dev; @@ -82,8 +89,11 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) pm_runtime_get_sync(dev->parent); spin_lock(&drvdata->spinlock); - /* no need to do anything if enabled or unpowered*/ - if (config->hw_enabled || !config->hw_powered) + /* no need to do anything if enabled or unpowered */ + if (!hp_re_enable) { + if (config->hw_enabled || !config->hw_powered) + goto cti_state_unchanged; + } else if (!atomic_read(&drvdata->config.enable_req_count)) goto cti_state_unchanged; /* claim the device */ @@ -91,7 +101,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) if (rc) goto cti_err_not_enabled; - if (drvdata->ctidev.cpu >= 0) { + if (drvdata->ctidev.cpu >= 0 && !hp_re_enable) { rc = smp_call_function_single(drvdata->ctidev.cpu, cti_enable_hw_smp_call, drvdata, 1); @@ -102,12 +112,15 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) } config->hw_enabled = true; - atomic_inc(&drvdata->config.enable_req_count); + if (!hp_re_enable) + atomic_inc(&drvdata->config.enable_req_count); + spin_unlock(&drvdata->spinlock); return rc; cti_state_unchanged: - atomic_inc(&drvdata->config.enable_req_count); + if (!hp_re_enable) + atomic_inc(&drvdata->config.enable_req_count); /* cannot enable due to error */ cti_err_not_enabled: @@ -563,12 +576,127 @@ static void cti_remove_conn_xrefs(struct cti_drvdata *drvdata) } } +/** cti PM callbacks **/ +static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, + void *v) +{ + struct cti_drvdata *drvdata; + unsigned int cpu = smp_processor_id(); + + if (!cti_cpu_drvdata[cpu]) + return NOTIFY_OK; + + drvdata = cti_cpu_drvdata[cpu]; + + if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu)) + return NOTIFY_BAD; + + switch (cmd) { + case CPU_PM_ENTER: + /* CTI regs all static - we have a copy & nothing to save */ + drvdata->config.hw_powered = false; + if (drvdata->config.hw_enabled) + coresight_disclaim_device(drvdata->base); + break; + + case CPU_PM_ENTER_FAILED: + drvdata->config.hw_powered = true; + if (drvdata->config.hw_enabled) { + if (coresight_claim_device(drvdata->base)) + drvdata->config.hw_enabled = false; + } + break; + + case CPU_PM_EXIT: + /* write hardware registers to re-enable. */ + drvdata->config.hw_powered = true; + drvdata->config.hw_enabled = false; + + /* check enable reference count to enable HW */ + if (atomic_read(&drvdata->config.enable_req_count)) { + /* check we can claim the device as we re-power */ + if (coresight_claim_device(drvdata->base)) + return NOTIFY_OK; + + drvdata->config.hw_enabled = true; + cti_write_all_hw_regs(drvdata); + } + break; + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +static struct notifier_block cti_cpu_pm_nb = { + .notifier_call = cti_cpu_pm_notify, +}; + +static int cti_cpu_pm_register(void) +{ + if (IS_ENABLED(CONFIG_CPU_PM)) + return cpu_pm_register_notifier(&cti_cpu_pm_nb); + + return 0; +} + +static void cti_cpu_pm_unregister(void) +{ + if (IS_ENABLED(CONFIG_CPU_PM)) + cpu_pm_unregister_notifier(&cti_cpu_pm_nb); +} + +/* CPU HP handlers */ +static int cti_starting_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + spin_lock(&drvdata->spinlock); + drvdata->config.hw_powered = true; + spin_unlock(&drvdata->spinlock); + + cti_enable_hw(drvdata, true); + return 0; +} + +static int cti_dying_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + spin_lock(&drvdata->spinlock); + drvdata->config.hw_powered = false; + coresight_disclaim_device(drvdata->base); + spin_unlock(&drvdata->spinlock); + return 0; +} + +/* release PM registrations */ +static void cti_pm_release(struct cti_drvdata *drvdata) +{ + if (drvdata->ctidev.cpu >= 0) { + if (--nr_cti_cpu == 0) { + cti_cpu_pm_unregister(); + + cpuhp_remove_state_nocalls( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING); + } + cti_cpu_drvdata[drvdata->ctidev.cpu] = NULL; + } +} + /** cti ect operations **/ int cti_enable(struct coresight_device *csdev) { struct cti_drvdata *drvdata = csdev_to_cti_drvdata(csdev); - return cti_enable_hw(drvdata); + return cti_enable_hw(drvdata, false); } int cti_disable(struct coresight_device *csdev) @@ -598,6 +726,7 @@ static void cti_device_release(struct device *dev) mutex_lock(&ect_mutex); cti_remove_conn_xrefs(drvdata); + cti_pm_release(drvdata); /* remove from the list */ list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) { @@ -673,6 +802,23 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) goto err_out; } + /* setup CPU power management handling for CPU bound CTI devices. */ + if (drvdata->ctidev.cpu >= 0) { + cti_cpu_drvdata[drvdata->ctidev.cpu] = drvdata; + if (!nr_cti_cpu++) { + cpus_read_lock(); + cpuhp_setup_state_nocalls_cpuslocked( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, + "arm/coresight_cti:starting", + cti_starting_cpu, cti_dying_cpu); + + ret = cti_cpu_pm_register(); + cpus_read_unlock(); + if (ret) + goto err_out; + } + } + /* create dynamic attributes for connections */ ret = cti_create_cons_sysfs(dev, drvdata); if (ret) { @@ -711,6 +857,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_out: + cti_pm_release(drvdata); return ret; } diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 77d70b633531..6dc7332307ca 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -142,6 +142,7 @@ enum cpuhp_state { CPUHP_AP_ARM_XEN_STARTING, CPUHP_AP_ARM_KVMPV_STARTING, CPUHP_AP_ARM_CORESIGHT_STARTING, + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, CPUHP_AP_ARM64_ISNDEP_STARTING, CPUHP_AP_SMPCFD_DYING, CPUHP_AP_X86_TBOOT_DYING, -- 2.17.1

4 years, 6 months

[PATCH] dt-bindings: qcom: Add CTI options for qcom msm8916

by Mike Leach

Adds system and CPU bound CTI definitions for Qualcom msm8916 platform (Dragonboard DB410C). System CTIs 2-11 are omitted as no information available at present. Tested on Linux 5.7-rc1. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a88a15f2352b..194d5e45f4e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/reset/qcom,gcc-msm8916.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/arm/coresight-cti-dt.h> / { interrupt-parent = <&intc>; @@ -1424,7 +1425,7 @@ cpu = <&CPU3>; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1443,7 +1444,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1462,7 +1463,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1481,7 +1482,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1500,6 +1501,82 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; -- 2.17.1

4 years, 6 months

"COVID-19: Face Masks & Hand Sanitizer"

by Joe Meese

Hello, Trying to get in contact with the purchasing team regarding face masks and hand sanitizer. We can urgently supply 3PY, N95, KN95, FFP2, FFP3, Hand Sanitizers, Gloves, Hazmat Suits at a great price. *Please check:* http://www.ppekits.net/supply/ Let me know if you have any questions. Thanks, -- Joe Meese - Director of Marketing The Dioz Group of Companies - Emergencyessentials Office in the UK, USA, Australia. HQ: 8730 Wilshire Blvd, Penthouse Beverly Hills, CA 90211 Free Call: 855 525 2642 You may unsubscribe <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/u?u=fb55153e-9c57…> to stop receiving our emails.

4 years, 6 months

[PATCH] perf: cs-etm: Update to build with latest opencsd version.

by Mike Leach

OpenCSD version v0.14.0 adds in a new output element. This is represented by a new value in the generic element type enum, which must be added to the handling code in perf cs-etm-decoder to prevent build errors due to build options on the perf project. This element is not currently used by the perf decoder. Tested on Linux 5.7-rc1. Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index cd92a99eb89d..da4737cbc2ab 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -564,6 +564,10 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( resp = cs_etm_decoder__set_tid(etmq, packet_queue, elem, trace_chan_id); break; + /* Unused packet types */ +#if OCSD_VER_NUM >= 0x0E00 + case OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH: +#endif case OCSD_GEN_TRC_ELEM_ADDR_NACC: case OCSD_GEN_TRC_ELEM_CYCLE_COUNT: case OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN: -- 2.17.1

4 years, 6 months

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