CoreSight

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2615 discussions

[PATCH v2 0/2] tools: Fix bitfield failure and minor polish

by Leo Yan

The first patch fixes an build failure issued caused by bitfield on the stable kernel, the second patch is a minor polish to avoid including redundant headers. Verified for Arm64 perf building. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (2): tools: Fix bitfield dependency failure perf: Remove redundant kernel.h include tools/include/linux/bitfield.h | 1 + tools/perf/arch/arm64/util/header.c | 1 - tools/perf/util/cs-etm.c | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) --- base-commit: 800af362d68945e589f73cda429d04bfe4287feb change-id: 20260123-perf_fix_bitfield-h-084902f55c35 Best regards, -- Leo Yan <leo.yan(a)arm.com>

16 hours, 46 minutes

Re: [PATCH v10 3/8] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Introduce sysfs_read_ops as a wrapper, wrap sysfs read operations, for reading > trace data from the TMC buffer. > > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tmc-core.c | 50 +++++++++++------------- > drivers/hwtracing/coresight/coresight-tmc.h | 17 ++++++++ > 2 files changed, 40 insertions(+), 27 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 1ea255ffa67c..8b0397a77e57 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -232,17 +232,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) > { > int ret = 0; > > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - ret = tmc_read_prepare_etb(drvdata); > - break; > - case TMC_CONFIG_TYPE_ETR: > - ret = tmc_read_prepare_etr(drvdata); > - break; > - default: > + if (drvdata->sysfs_ops) > + ret = drvdata->sysfs_ops->read_prepare(drvdata); > + else > ret = -EINVAL; > - } > > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); > @@ -254,17 +247,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata) > { > int ret = 0; > > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - ret = tmc_read_unprepare_etb(drvdata); > - break; > - case TMC_CONFIG_TYPE_ETR: > - ret = tmc_read_unprepare_etr(drvdata); > - break; > - default: > + if (drvdata->sysfs_ops) > + ret = drvdata->sysfs_ops->read_unprepare(drvdata); > + else > ret = -EINVAL; > - } > > if (!ret) > dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); > @@ -291,13 +277,8 @@ static int tmc_open(struct inode *inode, struct file *file) > static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, > char **bufpp) > { > - switch (drvdata->config_type) { > - case TMC_CONFIG_TYPE_ETB: > - case TMC_CONFIG_TYPE_ETF: > - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); > - case TMC_CONFIG_TYPE_ETR: > - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); > - } > + if (drvdata->sysfs_ops) > + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); minor nit: Please could we bail out in tmc_open() if the drvdata->sysfs_ops is not set. That way, we don't have to sprinkle it everywhere. And also, we don't expect to see this case anyways. > > return -EINVAL; > } > @@ -769,6 +750,18 @@ static void register_crash_dev_interface(struct tmc_drvdata *drvdata, > "Valid crash tracedata found\n"); > } > > +static const struct sysfs_read_ops tmc_etb_sysfs_read_ops = { minor nit: please could we rename the struct type to : struct tmc_sysfs_ops and then use etb_sysfs_ops = {} etr_sysfs_ops = {} Rest looks fine to me Suzuki > + .read_prepare = tmc_read_prepare_etb, > + .read_unprepare = tmc_read_unprepare_etb, > + .get_trace_data = tmc_etb_get_sysfs_trace, > +}; > + > +static const struct sysfs_read_ops tmc_etr_sysfs_read_ops = { > + .read_prepare = tmc_read_prepare_etr, > + .read_unprepare = tmc_read_unprepare_etr, > + .get_trace_data = tmc_etr_get_sysfs_trace, > +}; > + > static int __tmc_probe(struct device *dev, struct resource *res) > { > int ret = 0; > @@ -828,6 +821,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; > desc.ops = &tmc_etb_cs_ops; > dev_list = &etb_devs; > + drvdata->sysfs_ops = &tmc_etb_sysfs_read_ops; > break; > case TMC_CONFIG_TYPE_ETR: > desc.groups = coresight_etr_groups; > @@ -841,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > mutex_init(&drvdata->idr_mutex); > dev_list = &etr_devs; > INIT_LIST_HEAD(&drvdata->etr_buf_list); > + drvdata->sysfs_ops = &tmc_etr_sysfs_read_ops; > break; > case TMC_CONFIG_TYPE_ETF: > desc.groups = coresight_etf_groups; > @@ -849,6 +844,7 @@ static int __tmc_probe(struct device *dev, struct resource *res) > desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; > desc.ops = &tmc_etf_cs_ops; > dev_list = &etf_devs; > + drvdata->sysfs_ops = &tmc_etb_sysfs_read_ops; > break; > default: > pr_err("%s: Unsupported TMC config\n", desc.name); > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 9b3c4e6f0a5e..c9a82ff6cd00 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -221,6 +221,8 @@ struct etr_buf_node { > struct list_head node; > }; > > +struct sysfs_read_ops; > + > /** > * struct tmc_drvdata - specifics associated to an TMC component > * @atclk: optional clock for the core parts of the TMC. > @@ -258,6 +260,7 @@ struct etr_buf_node { > * Used by ETR/ETF. > * @etr_buf_list: List that is used to manage allocated etr_buf. > * @reading_node: Available buffer_node for byte-cntr reading. > + * @sysfs_ops: Read operations for sysfs mode. > */ > struct tmc_drvdata { > struct clk *atclk; > @@ -290,6 +293,20 @@ struct tmc_drvdata { > struct tmc_resrv_buf crash_mdata; > struct list_head etr_buf_list; > struct etr_buf_node *reading_node; > + const struct sysfs_read_ops *sysfs_ops; > +}; > + > +/** > + * struct sysfs_read_ops - read operations for TMC and its helper devices > + * @read_prepare: prepare operation. > + * @read_unprepare: unprepare operation. > + * @get_trace_data: read operation. > + */ > +struct sysfs_read_ops { > + int (*read_prepare)(struct tmc_drvdata *drvdata); > + int (*read_unprepare)(struct tmc_drvdata *drvdata); > + ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos, > + size_t len, char **bufpp); > }; > > struct etr_buf_operations { >

1 day, 20 hours

Re: [PATCH v10 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic

by Suzuki K Poulose

On 22/01/2026 02:08, Jie Gan wrote: > Remove ctcu_get_active_port from CTCU module and add it to the core > framework. > > The port number is crucial for the CTCU device to identify which ETR > it serves. With the port number we can correctly get required parameters > of the CTCU device in TMC module. > > Reviewed-by: Mike Leach <mike.leach(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +----------------- > drivers/hwtracing/coresight/coresight-priv.h | 2 ++ > 3 files changed, 27 insertions(+), 18 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index c660cf8adb1c..0e8448784c62 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -585,6 +585,30 @@ struct coresight_device *coresight_get_sink(struct coresight_path *path) > } > EXPORT_SYMBOL_GPL(coresight_get_sink); > > +/** > + * coresight_get_in_port: Find the input port number at @csdev where a @remote > + * device is connected to. This doesn't match the code ? We are looking at the remote devices' in_connections ? > + * > + * @csdev: csdev of the device. > + * @remote: csdev of the remote device which is connected to @csdev. > + * > + * Return: port number upon success or -EINVAL for fail. > + */ > +int coresight_get_in_port(struct coresight_device *csdev, > + struct coresight_device *remote) > +{ > + struct coresight_platform_data *pdata = remote->pdata; > + int i; > + > + for (i = 0; i < pdata->nr_inconns; ++i) { > + if (pdata->in_conns[i]->src_dev == csdev) > + return pdata->in_conns[i]->dest_port; > + } Suzuki

1 day, 20 hours

Re: [PATCH v5 0/3] Coresight TMC-ETR: refactor the tmc-etr mode and some cleanups

by Suzuki K Poulose

On Wed, 21 Jan 2026 18:15:40 +0800, Yushan Wang wrote: > This patchset builds upon Yicong's previous patches [1]. > I rebase the patchset onto coresight for-next branch. > > Patch 2 introducing fix race issues found by using TMC-ETR. > Patch 1 & 3 introducing two cleanups found when debugging the issues. > > [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… > > [...] Applied, thanks! [1/3] coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata https://git.kernel.org/coresight/c/5da8c55dd879 [2/3] coresight: tmc-etr: Fix race condition between sysfs and perf mode https://git.kernel.org/coresight/c/e6e43e82c79c [3/3] coresight: tmc: Decouple the perf buffer allocation from sysfs mode https://git.kernel.org/coresight/c/eebe8dbd8630 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 days, 13 hours

[PATCH v2 0/2] perf cs-etm: Fix decoding for sparse CPU maps

by James Clark

Fix a regression caused by an incorrect assumption about auxtrace indices. Then add a test that would have caught it. --- Changes in v2: - Fix cover letter and subject - Link to v1: https://lore.kernel.org/r/20260119-james-perf-coresight-cpu-map-segfault-v1… --- James Clark (2): perf cs-etm: Fix decoding for sparse CPU maps perf cs-etm: Test sparse CPU maps tools/perf/tests/shell/test_arm_coresight.sh | 54 ++++++++++++++++++++++++++++ tools/perf/util/cs-etm.c | 3 +- 2 files changed, 56 insertions(+), 1 deletion(-) --- base-commit: 571d29baa07e83e637075239f379f91353c24ec9 change-id: 20260115-james-perf-coresight-cpu-map-segfault-e250af5aa778 Best regards, -- James Clark <james.clark(a)linaro.org>

3 days, 9 hours

[PATCH] stm class: Fix Kconfig symbols

by Leo Yan

Kconfig symbols must not include the CONFIG_ prefix. Remove the CONFIG_ prefix for default values to work. Fixes: a02509f301c6 ("stm class: Factor out default framing protocol") Fixes: d69d5e83110f ("stm class: Add MIPI SyS-T protocol support") Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- drivers/hwtracing/stm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/stm/Kconfig b/drivers/hwtracing/stm/Kconfig index eda6b11d40a1f9ab49a1ec1e6faae8ee178c5ed3..cd7f0b0f3fbebc74775d8835187e49e5bd21d646 100644 --- a/drivers/hwtracing/stm/Kconfig +++ b/drivers/hwtracing/stm/Kconfig @@ -13,7 +13,7 @@ if STM config STM_PROTO_BASIC tristate "Basic STM framing protocol driver" - default CONFIG_STM + default STM help This is a simple framing protocol for sending data over STM devices. This was the protocol that the STM framework used @@ -28,7 +28,7 @@ config STM_PROTO_BASIC config STM_PROTO_SYS_T tristate "MIPI SyS-T STM framing protocol driver" - default CONFIG_STM + default STM help This is an implementation of MIPI SyS-T protocol to be used over the STP transport. In addition to the data payload, it --- base-commit: 40fbbd64bba6c6e7a72885d2f59b6a3be9991eeb change-id: 20251216-fix_stm_kconfig-a72f40c7612c Best regards, -- Leo Yan <leo.yan(a)arm.com>

4 days, 13 hours

Re: [PATCH v2 1/2] perf cs-etm: Fix decoding for sparse CPU maps

by Leo Yan

On Mon, Jan 19, 2026 at 02:11:43PM +0200, Adrian Hunter wrote: [...] > >> 0 0 0x200 [0x90]: PERF_RECORD_ID_INDEX nr: 4 > >> ... id: 771 idx: 0 cpu: 2 tid: -1 > >> ... id: 772 idx: 1 cpu: 3 tid: -1 > >> ... id: 773 idx: 0 cpu: 2 tid: -1 > >> ... id: 774 idx: 1 cpu: 3 tid: -1 > > > > Seems to me that this patch works around the issue by using the CPU ID > > instead, but event->auxtrace.idx is broken. > > > > Should we store the correct index in event->auxtrace.idx (e.g., in the > > __perf_event__synthesize_id_index()) ? > > The idx value represents a perf events ring buffer. Events on the same > CPU can share the same ring buffer. But in the case of per-thread > recording, different threads have different ring buffers and therefore > different idx values. > > So I don't think the idx value is wrong. It is just not the same thing > as CPU number. Thanks a lot for the explanation, this makes sense to me. Leo

4 days, 16 hours

[PATCH RESEND v5 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v5: - Add the missing review-by tag for patch 3. - Link to v4: https://lore.kernel.org/r/20250831-itnoc-v4-0-f0fb0ef822a5@oss.qualcomm.com Changes in v4: - Fix unintended blank line removals in trace_noc_enable_hw. - Link to v3: https://lore.kernel.org/r/20250828-itnoc-v3-0-f1b55dea7a27@oss.qualcomm.com Changes in v3: - Add detail for changes in V2. - Remove '#address-cells' and '#size-cells' properties from in-ports field. - Fix comment indentation for packet description. - Link to v2: https://lore.kernel.org/r/20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com Changes in v2: - Removed the trailing '|' after the description in qcom,coresight-itnoc.yaml. - Dropped the 'select' section from the YAML file. - Updated node name to use a more generic naming convention. - Removed the 'items' property from the compatible field. - Deleted the description for the reg property. - Dropped clock-names and adjusted the order of clock-names and clocks. - Moved additionalProperties to follow the $ref of out-ports. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 90 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 136 +++++++++++++++++++-- 2 files changed, 215 insertions(+), 11 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

4 days, 18 hours

Re: [PATCH] coresight: etm3x: Fix cpulocked warning on cpuhp

by Suzuki K Poulose

On Thu, 08 Jan 2026 16:24:27 +0100, Antonio Borneo wrote: > When changes [1] and [2] have been applied to the driver etm4x, the > same modifications have been also collapsed in [3] and applied in > one shot to the driver etm3x. > While doing this, the driver etm3x has not been aligned to etm4x on > the use of non cpuslocked version of cpuhp callback setup APIs. > > The current code triggers two run-time warnings when the kernel is > compiled with CONFIG_PROVE_LOCKING=y. > > [...] Applied, thanks! [1/1] coresight: etm3x: Fix cpulocked warning on cpuhp https://git.kernel.org/coresight/c/1feb0377b9b8 Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

4 days, 18 hours

[PATCH 0/2] (no cover subject)

by James Clark

--- James Clark (2): perf cs-etm: Fix decoding for sparse CPU maps perf cs-etm: Test sparse CPU maps tools/perf/tests/shell/test_arm_coresight.sh | 54 ++++++++++++++++++++++++++++ tools/perf/util/cs-etm.c | 3 +- 2 files changed, 56 insertions(+), 1 deletion(-) --- base-commit: 571d29baa07e83e637075239f379f91353c24ec9 change-id: 20260115-james-perf-coresight-cpu-map-segfault-e250af5aa778 Best regards, -- James Clark <james.clark(a)linaro.org>

4 days, 20 hours

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