CoreSight

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[PATCH v2 00/28] CoreSight: Address CPU Power Management Issues

by Leo Yan

This series addresses CPU power management issues in the CoreSight drivers. For easier review, the patches are organized into two categories: o Patches 01 ~ 10 focus on CPU power management within the ETM drivers. These patches fix SMP-safe access to the mode, correct context synchronization, and refactor the CPU suspend/resume flows. o Patches 11 ~ 28 extend CPU power management to cover activated paths, including helpers, links, and sinks. These changes move CPU PM and hotplug notifiers from the ETMv4 driver into the CoreSight core layer. Summary of Changes: - Patches 01 ~ 03: Fix device mode access in the SMP mode. - Patch 04 : A minor fix for polling bit. - Patches 05 ~ 07: Improve the context synchronization based on the ETM specification (IHI0064H.b) and Arm ARM (ARM DDI 0487 L.a). - Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4 driver, in the end, the CPU PM callbacks reuse the normal enabling and disabling flows. - Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer. - Patches 18 ~ 25: Enhance device mode handling in the CTI driver, distinguishes debug mode from trace modes (Perf or SysFS mode). Extend support activated paths during CPU idle. Support save and restore context for per-CPU sink (TRBE). - Patches 26 ~ 28: Move CPU hotplug notifier from the ETMv4 driver to the core layer. The full path is now managed in CPU hotplug. Verification: This series has been verified on the following platforms: - Hikey960, Juno-r0 and Juno-r2: Note that the firmware on Hikey960 and Juno-r0 is unstable. While no CoreSight failures were observed, but the CPU hotplug or CPU idle itself may fail intermittently. Juno-r2 is much stable and can pass 24+ hours stress test. - FVP RevC: Verified TRBE changes. Stress test script: #!/usr/bin/bash echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink while true; do echo 0 > /sys/devices/system/cpu/cpu2/online; echo 1 > /sys/devices/system/cpu/cpu2/online; done & while true; do echo 1 > /sys/bus/coresight/devices/etm2/enable_source; echo 0 > /sys/bus/coresight/devices/etm2/enable_source; done & --- Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (27): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Ensure context synchronization is not ignored coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Reuse normal enable and disable logic in CPU idle coresight: Populate CPU ID into the coresight_device structure coresight: sysfs: Validate CPU online status for per-CPU sources coresight: Set per CPU source pointer coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: Add callback to determine if context save/restore is needed coresight: etm4x: Remove redundant condition checks in save and restore coresight: cti: Fix race condition by using device mode coresight: cti: Introduce CS_MODE_DEBUG mode coresight: cti: Properly handle modes in CPU PM notifiers coresight: Add per-CPU path pointer coresight: Add 'in_idle' argument to path enable/disable functions coresight: Control path during CPU idle coresight: Add PM callbacks for percpu sink coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: Move CPU hotplug callbacks to core layer coresight: Manage activated path during CPU hotplug Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + drivers/hwtracing/coresight/coresight-cti-core.c | 40 +- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + drivers/hwtracing/coresight/coresight-etm3x-core.c | 61 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 488 ++++++--------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 --- drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 10 + drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 1 + drivers/hwtracing/coresight/coresight-tpdm.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++ drivers/hwtracing/coresight/ultrasoc-smb.c | 1 + include/linux/coresight.h | 55 ++- 21 files changed, 665 insertions(+), 487 deletions(-) --- base-commit: 66701750d5565c574af42bef0b789ce0203e3071 change-id: 20250611-arm_cs_pm_fix_v3-f4ae29bb7d81 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 days

Re: [PATCH v2 0/3] coresight-tnoc: Add support for Interconnect TNOC

by yuanfang zhang

On 8/19/2025 7:30 PM, Krzysztof Kozlowski wrote: > On 19/08/2025 12:27, Yuanfang Zhang wrote: >> This patch series adds support for the Qualcomm CoreSight Interconnect TNOC >> (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding >> trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, >> this block does not support aggregation or ATID assignment. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> Changes in v2: >> - Refactor the dt-binding file. > > Everything is rafactor. What changed specifically? > > Or you just ignored prevous feedback and did other changes? > The feedback has not been ignored, i will update the detail in next patch. > > > Best regards, > Krzysztof

4 days, 7 hours

Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/20/2025 3:45 AM, Rob Herring wrote: > On Tue, Aug 19, 2025 at 03:27:43AM -0700, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Network On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++++++++++ >> 1 file changed, 96 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..a3b5f2b949f69617a014d0ae2831c9c767178f8c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> @@ -0,0 +1,96 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC >> + >> +maintainers: >> + - Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> + >> +description: >> + The Interconnect TNOC is a CoreSight graph link that forwards trace data >> + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it >> + does not have aggregation and ATID functionality. >> + >> +properties: >> + $nodename: >> + pattern: "^itnoc(@[0-9a-f]+)?$" >> + >> + compatible: >> + const: qcom,coresight-itnoc >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: apb >> + >> + in-ports: >> + $ref: /schemas/graph.yaml#/properties/ports > >> + properties: >> + '#address-cells': >> + const: 1 >> + '#size-cells': >> + const: 0 > > Drop these. Already defined by the above ref. > sure, will update. >> + >> + patternProperties: >> + '^port(@[0-9a-f]{1,2})?$': >> + description: Input connections from CoreSight Trace Bus >> + $ref: /schemas/graph.yaml#/properties/port >> + >> + out-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + additionalProperties: false >> + >> + properties: >> + port: >> + description: out connections to aggregator TNOC >> + $ref: /schemas/graph.yaml#/properties/port >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - in-ports >> + - out-ports >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + itnoc@109ac000 { >> + compatible = "qcom,coresight-itnoc"; >> + reg = <0x109ac000 0x1000>; >> + >> + clocks = <&aoss_qmp>; >> + clock-names = "apb"; >> + >> + in-ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + port@0 { >> + reg = <0>; >> + tn_ic_in_tpdm_dcc: endpoint { >> + remote-endpoint = <&tpdm_dcc_out_tn_ic>; >> + }; >> + }; >> + }; >> + >> + out-ports { >> + port { >> + tn_ic_out_tnoc_aggr: endpoint { >> + /* to Aggregator TNOC input */ >> + remote-endpoint = <&tn_ag_in_tn_ic>; >> + }; >> + }; >> + }; >> + }; >> +... >> >> -- >> 2.34.1 >>

4 days, 7 hours

Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/19/2025 8:32 PM, Rob Herring (Arm) wrote: > > On Tue, 19 Aug 2025 03:27:43 -0700, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Network On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++++++++++ >> 1 file changed, 96 insertions(+) >> > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250819-itn… > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > Below is my dtschema and yamllint version, They should already be the latest version. Name: dtschema Version: 2025.8 Name: yamllint Version: 1.37.1 I ran below 'make dt_binding_check', don't get any error/warnings. make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml

4 days, 7 hours

[PATCH v2 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Changes in v2: - Refactor the dt-binding file. - Change "atid" type from u32 to int, set it as "-EOPNOTSUPP" for non-AMBA device. - Link to v1: https://lore.kernel.org/r/20250815-itnoc-v1-0-62c8e4f7ad32@oss.qualcomm.com --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 96 ++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 147 ++++++++++++++++++--- 2 files changed, 226 insertions(+), 17 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

5 days, 3 hours

[PATCH 0/3] coresight-tnoc: Add support for Interconnect TNOC

by Yuanfang Zhang

This patch series adds support for the Qualcomm CoreSight Interconnect TNOC (Trace Network On Chip) block, which acts as a CoreSight graph link forwarding trace data from subsystems to the Aggregator TNOC. Unlike the Aggregator TNOC, this block does not support aggregation or ATID assignment. Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> --- Yuanfang Zhang (3): dt-bindings: arm: qcom: Add Coresight Interconnect TNOC coresight-tnoc: add platform driver to support Interconnect TNOC coresight-tnoc: Add runtime PM support for Interconnect TNOC .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.c | 179 +++++++++++++++------ 2 files changed, 240 insertions(+), 47 deletions(-) --- base-commit: 2b52cf338d39d684a1c6af298e8204902c026aca change-id: 20250815-itnoc-460273d1b80c Best regards, -- Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com>

5 days, 5 hours

Re: [PATCH 1/3] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC

by yuanfang zhang

On 8/16/2025 4:33 PM, Krzysztof Kozlowski wrote: > On 15/08/2025 15:18, Yuanfang Zhang wrote: >> Add device tree binding for Qualcomm Coresight Interconnect Trace >> Netwrok On Chip (ITNOC). This TNOC acts as a CoreSight >> graph link that forwards trace data from a subsystem to the >> Aggregator TNOC, without aggregation or ATID functionality. >> >> Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> --- >> .../bindings/arm/qcom,coresight-itnoc.yaml | 108 +++++++++++++++++++++ >> 1 file changed, 108 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> new file mode 100644 >> index 0000000000000000000000000000000000000000..fd224e07ce68918b453210763aacda585d5a5ca2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml >> @@ -0,0 +1,108 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Interconnect Trace Network On Chip - ITNOC >> + >> +maintainers: >> + - Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> >> + >> +description: | > Do not need '|' unless you need to preserve formatting. sure, will remove it. >> + The Interconnect TNOC is a CoreSight graph link that forwards trace data >> + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it >> + does not have aggregation and ATID functionality. >> + >> +select: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,coresight-itnoc >> + required: >> + - compatible > Why all this? Drop sure. >> + >> +properties: >> + $nodename: >> + pattern: "^tnoc(@[0-9a-f]+)?$" > Why are you requiring a non-generic name? will update the name. >> + >> + compatible: >> + items: > No need for items sure, will remove it. >> + - const: qcom,coresight-itnoc >> + >> + reg: >> + maxItems: 1 >> + description: Base address and size of the ITNOC registers. > Drop, redundant sure, will remove it. >> + >> + clock-names: >> + items: >> + - const: apb > Drop clock-names, obvious. Also, odd order - names are never before > actual property. sure, will update the order. >> + >> + clocks: >> + maxItems: 1 >> + >> + in-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + '#address-cells': >> + const: 1 >> + '#size-cells': >> + const: 0 >> + >> + patternProperties: >> + '^port(@[0-9a-f]{1,2})?$': > Why do you have here 255 ports? It supports a maximum of 256 input ports, so it is limited to 0-255. >> + description: Input connections from CoreSight Trace Bus >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after $ref sure, will update. >> + >> + out-ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + >> + properties: >> + port: >> + description: out connections to aggregator TNOC >> + $ref: /schemas/graph.yaml#/properties/port >> + additionalProperties: false > This goes after ref sure, will update. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names > And here different order... Be consistent. See also DTS coding style. sure, will update the order. >> + - in-ports >> + - out-ports >> + >> +additionalProperties: false >> + > > > Best regards, > Krzysztof

6 days, 4 hours

[PATCH v3 0/3] Coresight TMC-ETR some bugfixes and cleanups

by Junhao He

This patchset builds upon Yicong's previous patches [1]. Introducing fix two race issues found by using TMC-ETR and CATU, Two cleanups found when debugging the issues. [1] https://lore.kernel.org/linux-arm-kernel/20241202092419.11777-1-yangyicong@… --- Changes in v3: - Patches 1: Additional comment for tmc_drvdata::etr_mode. Update comment for tmc_drvdata::reading with Jonathan's Tag. - Patches 2: Replace scoped_guard with guard with Jonathan's Tag. - Patches 2: Fix spinlock to raw_spinlock, and refactor this code based on Leo's suggested solution. - Patches 3: change the size's type to ssize_t and use max_t to simplify the code with Leo's Tag. Link: https://lore.kernel.org/linux-arm-kernel/20250620075412.952934-1-hejunhao3@… Changes in v2: - Updated the commit of patch2. - Rebase to v6.16-rc1 Junhao He (1): coresight: tmc: refactor the tmc-etr mode setting to avoid race conditions Yicong Yang (2): coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata coresight: tmc: Decouple the perf buffer allocation from sysfs mode .../hwtracing/coresight/coresight-tmc-etr.c | 110 ++++++++---------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + 2 files changed, 53 insertions(+), 59 deletions(-) -- 2.33.0

6 days, 5 hours

[PATCH v11 0/2] coresight: Add label sysfs node support

by Mao Jinlong

Change since V10: 1. Update kernel version to 6.18 V10 link: https://lkml.org/lkml/2025/8/6/520 Change since V9: 1. Replace scnprintf with sysfs_emit. 2. Update date in ABI files. V9 link: https://lkml.org/lkml/2025/7/17/832 Change since V8: 1. Add label in all documentations of coresight components. 2. Add control of the visibility of the label sysfs attribute. V8 link: https://lkml.org/lkml/2025/7/3/985 Change since V7: 1. Update the conflict when apply to coresight next. 2. Update the Date and version in ABI file. V7 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250226121926.… Change since V6: 1. Update the date and version in ABI file. Change since V5: 1. Update the kernel version of ABI files. 2. Add link of different patch versions. V5 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20241210122253.319… Change since V4: 1. Add label in DT and add label sysfs node for each coresight device. V4 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240703122340.268… Change since V3: 1. Change device-name to arm,cs-dev-name. 2. Add arm,cs-dev-name to only CTI and sources' dt-binding. V3 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240131082628.628… Change since V2: 1. Fix the error in coresight core. drivers/hwtracing/coresight/coresight-core.c:1775:7: error: assigning to 'char *' from 'const char *' discards qualifiers 2. Fix the warning when run dtbinding check. Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml: device-name: missing type definition V2 link: https://patchwork.kernel.org/project/linux-arm-msm/cover/20240115164252.265… Change since V1: 1. Change coresight-name to device name. 2. Add the device-name in coresight dt bindings. V1 link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230208110716.… Mao Jinlong (2): dt-bindings: arm: Add label in the coresight components coresight: Add label sysfs node support .../testing/sysfs-bus-coresight-devices-cti | 6 ++ .../sysfs-bus-coresight-devices-dummy-source | 6 ++ .../testing/sysfs-bus-coresight-devices-etb10 | 6 ++ .../testing/sysfs-bus-coresight-devices-etm3x | 6 ++ .../testing/sysfs-bus-coresight-devices-etm4x | 6 ++ .../sysfs-bus-coresight-devices-funnel | 6 ++ .../testing/sysfs-bus-coresight-devices-stm | 6 ++ .../testing/sysfs-bus-coresight-devices-tmc | 6 ++ .../testing/sysfs-bus-coresight-devices-tpdm | 6 ++ .../testing/sysfs-bus-coresight-devices-trbe | 6 ++ .../bindings/arm/arm,coresight-cti.yaml | 4 ++ .../arm/arm,coresight-dummy-sink.yaml | 4 ++ .../arm/arm,coresight-dummy-source.yaml | 4 ++ .../arm/arm,coresight-dynamic-funnel.yaml | 4 ++ .../arm/arm,coresight-dynamic-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-etb10.yaml | 4 ++ .../bindings/arm/arm,coresight-etm.yaml | 4 ++ .../arm/arm,coresight-static-funnel.yaml | 4 ++ .../arm/arm,coresight-static-replicator.yaml | 4 ++ .../bindings/arm/arm,coresight-tmc.yaml | 4 ++ .../bindings/arm/arm,coresight-tpiu.yaml | 4 ++ .../bindings/arm/qcom,coresight-ctcu.yaml | 4 ++ .../arm/qcom,coresight-remote-etm.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpda.yaml | 4 ++ .../bindings/arm/qcom,coresight-tpdm.yaml | 4 ++ drivers/hwtracing/coresight/coresight-sysfs.c | 71 ++++++++++++++++++- 26 files changed, 189 insertions(+), 2 deletions(-) -- 2.34.1

1 week, 1 day

[PATCH 0/6] coresight: Add format attribute for setting the timestamp interval

by James Clark

Do some cleanups then add a new format attribute to set the timestamp interval for ETMv4 in Perf mode. The current interval is too high for most use cases, and particularly on the FVP the number of timestamps generated is excessive. Although it would be good to make only SYNC timestamps the default and have counter timestamps opt-in, this would be a breaking change. We can always do that later, or disable counter timestamps from Perf. This is added as an event format attribute, rather than a Coresight config because it's something that the driver is already configuring automatically in Perf mode with any unused counter, so it's not possible to modify this with a config. Applies to coresight/next Signed-off-by: James Clark <james.clark(a)linaro.org> --- James Clark (6): coresight: Change syncfreq to be a u8 coresight: Fix holes in struct etmv4_config coresight: Repack struct etmv4_drvdata coresight: Refactor etm4_config_timestamp_event() coresight: Add format attribute for setting the timestamp interval coresight: docs: Document etm4x ts_interval Documentation/trace/coresight/coresight.rst | 14 +++ drivers/hwtracing/coresight/coresight-etm-perf.c | 6 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 110 +++++++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 86 ++++++++++------ 4 files changed, 144 insertions(+), 72 deletions(-) --- base-commit: a80198ba650f50d266d7fc4a6c5262df9970f9f2 change-id: 20250724-james-cs-syncfreq-7c2257a38ed3 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 3 days

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