CoreSight

coresight@lists.linaro.org

6 participants
2368 discussions

[PATCH v1 00/11] CoreSight: Refactor CPU PM and hotplug

by Leo Yan

Besides managing tracers (ETM) in CPU PM and hotplug flows, the CoreSight framework is found the issues below: Firstly, on some hardware platforms, CoreSight links (e.g., funnels and replicators, etc) reside in a cluster power domain. If the cluster is powered off, the link components also will lose their context. In this case, Arm CoreSight drivers report errors when detect unpaired self-host claim tags. Secondly, if a path has been activated from per CPU's tracer (ETM) to links and a sink in Sysfs mode, then when the CPU is hot-plugged off, only the associated ETM will be disabled. Afterwards, the links and the sink always keep on and no chance to be disabled. The last issue was reported by Yabin Cui (Google) that the TRBE driver misses to save and restore context during CPU low power states. As a result, it may cause hardware lockup issue on some devices. To resolve the power management issues, this series extends CPU power management to cover the entire activated path, including links and sinks. It moves CPU PM and hotplug notifiers from the ETMv4 driver to the CoreSight core layer. The core layer has sufficient info to maintain activated paths and can traverse the entire path to manipulate CoreSight modules accordingly. Patch 01 is to fix a bug in ETMv4 save and restore callbacks. Patches 02 ~ 06 move CPU PM code from ETMv4 driver to the core layer, and extends to maintain activated paths and control links. Patches 07 and 08 support save and restore context for per-CPU sink (TRBE). Note, for avoid long latency, system level's sinks in an activated path are not touched during CPU suspend and resume. Patches 09 ~ 11 move CPU hotplug notifier from ETMv4 driver to the core layer. The entire path will be controlled if the corresponding CPU is hot-plugged on or off. This series has been verified on Hikey960 for CPUIdle and hotplug. And it is tested on FVP for verifying TRBE with idle states. Leo Yan (10): coresight: etm4x: Control the trace unit in CPU suspend coresight: Set per CPU source pointer coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: Save activated path into source device coresight: Control path during CPU PM coresight: Add PM callbacks in sink operation coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: Move CPU hotplug callbacks to core layer coresight: Manage activated paths during CPU hotplug Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state drivers/hwtracing/coresight/coresight-core.c | 252 +++++++++++++++++++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 + drivers/hwtracing/coresight/coresight-etm4x-core.c | 133 ++++++---------------- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-sysfs.c | 12 +- drivers/hwtracing/coresight/coresight-trbe.c | 65 +++++++++++ include/linux/coresight.h | 11 ++ 7 files changed, 375 insertions(+), 101 deletions(-) -- 2.34.1

15 hours, 46 minutes

[PATCH 0/2] coresight: Dismiss smatch warnings

by Leo Yan

This series polishes the code to address warnings reported by the smatch static checker. Smatch reports a error "Function too hairy" for etm4x_sysreg_read() and etm4x_sysreg_write(). This is a trade off to avoid large code blocks, the implementation encapsulates logic using nested macros. But this is not friendly to static checker. For now, the code will be kept as is. Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (2): coresight: stm: Remove redundant NULL checks coresight: perf: Use %px for printing pointers drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++-- drivers/hwtracing/coresight/coresight-stm.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250611-arm_cs_fix_smatch_warning_v1-6c2b5e78e38a Best regards, -- Leo Yan <leo.yan(a)arm.com>

6 days, 21 hours

Re: [PATCH v2] coresight: fix indentation error in cscfg_remove_owned_csdev_configs()

by Leo Yan

On Wed, Jun 11, 2025 at 11:30:25AM +0100, Yeoreum Yun wrote: > Fix wrong indentation in cscfg_remove_owned_csdev_configs() > > Reported-by: kernel test robot <lkp(a)intel.com> > Closes: https://lore.kernel.org/oe-kbuild-all/202506102238.XQfScl5x-lkp@intel.com/ > Fixes: 53b9e2659719 ("coresight: holding cscfg_csdev_lock while removing cscfg from csdev") > Signed-off-by: Yeoreum Yun <yeoreum.yun(a)arm.com> Reviewed-by: Leo Yan <leo.yan(a)arm.com> > --- > > Sorry for my bad forgetting to run checkpatch.pl... > > --- > drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c > index 83dad24e0116..6836b05986e8 100644 > --- a/drivers/hwtracing/coresight/coresight-syscfg.c > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c > @@ -395,7 +395,7 @@ static void cscfg_remove_owned_csdev_configs(struct coresight_device *csdev, voi > if (list_empty(&csdev->config_csdev_list)) > return; > > - guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock); > + guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock); > > list_for_each_entry_safe(config_csdev, tmp, &csdev->config_csdev_list, node) { > if (config_csdev->config_desc->load_owner == load_owner) > -- > LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} >

1 week

[PATCH v9 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v9: - Mention the binding is only for Aggregator TNOC. - Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com Changes in v8: - Add sysfs node to expose atid. - Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ 4 files changed, 369 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 week

[PATCH v10 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v10: - Rebase to coresight/next branch. - Link to v9: https://lore.kernel.org/r/20250611-trace-noc-v9-0-4322d4cf8f4b@quicinc.com Changes in v9: - Mention the binding is only for Aggregator TNOC. - Link to v8: https://lore.kernel.org/r/20250606-trace-noc-v8-0-833f94712c57@quicinc.com Changes in v8: - Add sysfs node to expose atid. - Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++ drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ 4 files changed, 368 insertions(+) --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 week

[PATCH v3 0/9] coresight: Fix and improve clock usage

by Leo Yan

This series fixes and improves clock usage in the Arm CoreSight drivers. Based on the DT binding documents, the trace clock (atclk) is defined in some CoreSight modules, but support is absent. In most cases, the issue is hidden because the atclk clock is shared by multiple CoreSight modules and the clock is enabled anyway by other drivers. The first three patches address this issue. The programming clock (pclk) management in CoreSight drivers does not use the devm_XXX() variant APIs, the drivers needs to manually disable and release clocks for errors and for normal module exit. However, the drivers miss to disable clocks during module exit. The atclk may also not be disabled in CoreSight drivers during module exit. By using devm APIs, patches 04 and 05 fix clock disabling issues. Another issue is pclk might be enabled twice in init phase - once by AMBA bus driver, and again by CoreSight drivers. This is fixed in patch 06. Patches 07 to 09 refactor the clock related code. Patch 07 consolidats the clock initialization into a central place. Patch 08 makes the clock enabling sequence consistent. Patch 09 removes redundant condition checks and adds error handling in runtime PM. This series has been verified on Arm64 Hikey960 and Juno platforms. Changes from v2: - Updated subjects for patches 04 and 05 (Anshuman). - Refined condition checking "if (dev_is_amba(dev))" in patch 07 (Anshuman). Changes from v1: - Moved the coresight_get_enable_clocks() function into CoreSight core layer (James). - Added comments for clock naming "apb_pclk" and "apb" (James). - Re-ordered patches for easier understanding (Anshuman). - Minor improvement for commit log in patch 01 (Anshuman). Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (9): coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Appropriately disable programming clocks coresight: Appropriately disable trace bus clocks coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Make clock sequence consistent coresight: Refactor runtime PM drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++--------- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 45 +++++++++++++++ drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++--------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++----- drivers/hwtracing/coresight/coresight-etb10.c | 18 ++---- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++---- drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 66 ++++++++-------------- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++------------- drivers/hwtracing/coresight/coresight-stm.c | 34 +++++------ drivers/hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++-------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 36 +++++------- include/linux/coresight.h | 30 +--------- 16 files changed, 225 insertions(+), 289 deletions(-) --- base-commit: 408c97c4a5e0b634dcd15bf8b8808b382e888164 change-id: 20250609-arm_cs_fix_clock_v3_public-d546e8bfc852 Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 week, 1 day

[PATCH] coresight: trbe: Add ISB after TRBLIMITR write

by James Clark

DEN0154 states that hardware will be allowed to ignore writes to TRB* registers while the trace buffer is enabled. Add an ISB to ensure that it's disabled before clearing the other registers. This is purely defensive because it's expected that arm_trbe_disable() would be called before teardown which has the required ISB. Fixes: a2b579c41fe9 ("coresight: trbe: Remove redundant disable call") Signed-off-by: James Clark <james.clark(a)linaro.org> --- drivers/hwtracing/coresight/coresight-trbe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 8267dd1a2130..10f3fb401edf 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -257,6 +257,7 @@ static void trbe_drain_and_disable_local(struct trbe_cpudata *cpudata) static void trbe_reset_local(struct trbe_cpudata *cpudata) { write_sysreg_s(0, SYS_TRBLIMITR_EL1); + isb(); trbe_drain_buffer(); write_sysreg_s(0, SYS_TRBPTR_EL1); write_sysreg_s(0, SYS_TRBBASER_EL1); --- base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 change-id: 20250609-james-cs-trblimitr-isb-523f20d874d6 Best regards, -- James Clark <james.clark(a)linaro.org>

1 week, 1 day

[PATCH v8 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v8: - Add sysfs node to expose atid. - Link to v7: https://lore.kernel.org/r/20250523-trace-noc-v7-0-d65edbab2997@quicinc.com Changes in v7: - Move the content in header file into coresight-tnoc.c. - Use scoped_guard() to replace spin_lock(). - Invoke coresight_trace_id_put_system_id() for registration failure. - Link to v6: https://lore.kernel.org/r/20250522-trace-noc-v6-0-f5a9bcae90ee@quicinc.com Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ 4 files changed, 367 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 week, 2 days

[PATCH v6 0/2] coresight: Add Coresight Trace Network On Chip driver

by Yuanfang Zhang

The Trace Network On Chip (TNOC) is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace from subsystems and transfers it to coresight sink. In addition to the generic TNOC mentioned above, there is also a special type of TNOC called Interconnect TNOC. Unlike the generic TNOC, the Interconnect TNOC doesn't need ATID. Its primary function is to connect the source of subsystems to the Aggregator TNOC. Its driver is different from this patch and will describe it and upstream its driver separately. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- Changes in v6: - Add a newline after return statements. - Use 'x &= foo' to replace 'x = x & foo'. - Use 'x |= foo' to replace 'x = x | foo'. - Link to v5: https://lore.kernel.org/r/20250512-trace-noc-v5-0-f2ef070baee5@quicinc.com Changes in v5: - update cover-letter to describe the Interconnect TNOC. - Link to v4: https://lore.kernel.org/r/20250415-trace-noc-v4-0-979938fedfd8@quicinc.com Changes in v4: - Fix dt_binding warning. - update mask of trace_noc amba_id. - Modify driver comments. - rename TRACE_NOC_SYN_VAL to TRACE_NOC_SYNC_INTERVAL. - Link to v3: https://lore.kernel.org/r/20250411-trace-noc-v3-0-1f19ddf7699b@quicinc.com Changes in v3: - Remove unnecessary sysfs nodes. - update commit messages. - Use 'writel' instead of 'write_relaxed' when writing to the register for the last time. - Add trace_id ops. - Link to v2: https://lore.kernel.org/r/20250226-trace-noc-driver-v2-0-8afc6584afc5@quici… Changes in v2: - Modified the format of DT binging file. - Fix compile warnings. - Link to v1: https://lore.kernel.org/r/46643089-b88d-49dc-be05-7bf0bb21f847@quicinc.com --- Yuanfang Zhang (2): dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 111 ++++++++++++ drivers/hwtracing/coresight/Kconfig | 13 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 192 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tnoc.h | 34 ++++ 5 files changed, 351 insertions(+) --- base-commit: a2cc6ff5ec8f91bc463fd3b0c26b61166a07eb11 change-id: 20250403-trace-noc-f8286b30408e Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

1 week, 5 days

[PATCH] coresight-tpdm: add trace_id sysfs node

by Yuanfang Zhang

The trace ID of TPMD is the trace ID of the TPDA or TNOC which it is connected to, this change adds trace_id sysfs node to expose this trace id to userspace. Signed-off-by: Yuanfang Zhang <quic_yuanfang(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-tpdm.c | 16 ++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 7214e65097ec9ac69f6c7c9278bcd28d25945c9e..8a5d115157924f39b09f8e3005827d7d64aa376c 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -497,6 +497,9 @@ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, __tpdm_enable(drvdata); drvdata->enable = true; + + if (path) + drvdata->traceid = path->trace_id; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); @@ -554,6 +557,7 @@ static void tpdm_disable(struct coresight_device *csdev, __tpdm_disable(drvdata); coresight_set_mode(csdev, CS_MODE_DISABLED); drvdata->enable = false; + drvdata->traceid = 0; spin_unlock(&drvdata->spinlock); dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); @@ -655,9 +659,21 @@ static ssize_t integration_test_store(struct device *dev, } static DEVICE_ATTR_WO(integration_test); +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->traceid; + return sprintf(buf, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + static struct attribute *tpdm_attrs[] = { &dev_attr_reset_dataset.attr, &dev_attr_integration_test.attr, + &dev_attr_traceid.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index b117543897344b689f666f6890cabb59c8ee4869..e12a64f265daa86f1b82fa3640e271e8386f99af 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -300,6 +300,7 @@ struct cmb_dataset { * @cmb Specifics associated to TPDM CMB. * @dsb_msr_num Number of MSR supported by DSB TPDM * @cmb_msr_num Number of MSR supported by CMB TPDM + * @traceid: Value of the current ID for this component. */ struct tpdm_drvdata { @@ -313,6 +314,7 @@ struct tpdm_drvdata { struct cmb_dataset *cmb; u32 dsb_msr_num; u32 cmb_msr_num; + u8 traceid; }; /* Enumerate members of various datasets */ --- base-commit: 94305e83eccb3120c921cd3a015cd74731140bac change-id: 20250523-showtraceid-2df91c89be8f Best regards, -- Yuanfang Zhang <quic_yuanfang(a)quicinc.com>

2 weeks, 5 days

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