CoreSight

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[GIT PULL v2] coresight: updates for v6.2

by Suzuki K Poulose

Hi Greg, Please find the updated pull request with coresight updates to v6.2. Kindly consider pulling. Changes: - Fix empty lines around "Fixes" tag in the CTI Fix. Thanks Suzuki The following changes since commit 30a0b95b1335e12efef89dd78518ed3e4a71a763: Linux 6.1-rc3 (2022-10-30 15:19:28 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.2 for you to fetch changes up to c767c34740132ffc478226864a7461493cdc2413: coresight: etm4x: fix repeated words in comments (2022-11-28 18:29:53 +0000) ---------------------------------------------------------------- coresight: Update for v6.2 CoreSight updatesfor v6.2 includes : - Support for ETMv4 probing on hotplugged CPUs - Fix TRBE driver for cpuhp state refcounting - Fix CTI driver NULL pointer dereferencing - Fix comment for repeated word Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Jilin Yuan (1): coresight: etm4x: fix repeated words in comments Mike Leach (1): coresight: cti: Fix null pointer error on CTI init before ETM Tamas Zsoldos (1): coresight: etm4x: add CPU hotplug support for probing Yang Shen (1): coresight: trbe: remove cpuhp instance node before remove cpuhp state drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 155 +++++++++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 1 + 3 files changed, 116 insertions(+), 42 deletions(-)

1 year, 11 months

Re: [GIT PULL] coresight: updates for v6.2

by Suzuki K Poulose

Hi Greg On 28/11/2022 18:17, Greg KH wrote: > On Mon, Nov 28, 2022 at 03:17:35PM +0000, Suzuki K Poulose wrote: >> Hi Greg, >> >> Please find the coresight updates for Linux v6.2. Kindly consider pulling. >> >> Suzuki >> >> >> The following changes since commit 30a0b95b1335e12efef89dd78518ed3e4a71a763: >> >> Linux 6.1-rc3 (2022-10-30 15:19:28 -0700) >> >> are available in the Git repository at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.2 > > I get the following error when trying to push this out: > > Commit: bd7e9cef2137 ("coresight: cti: Fix null pointer error on CTI init before ETM") > Fixes tag: Fixes: 23722fb46725 ("coresight: Fix possible deadlock with lock dependency") > Has these problem(s): > - empty lines surround the Fixes tag Apologies. Will fix it. Is there a way to detect these issues at my end to avoid these issues ? I would be happy to improve the filtering at my side to save your cycles. Thanks Suzuki > > Please fix up and resend. > > thanks, > > greg k-h

1 year, 11 months

[GIT PULL] coresight: updates for v6.2

by Suzuki K Poulose

Hi Greg, Please find the coresight updates for Linux v6.2. Kindly consider pulling. Suzuki The following changes since commit 30a0b95b1335e12efef89dd78518ed3e4a71a763: Linux 6.1-rc3 (2022-10-30 15:19:28 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.2 for you to fetch changes up to 4ce71fdc8325936fd0d9ee819b8b18e1fc09bb2e: coresight: etm4x: fix repeated words in comments (2022-11-28 14:56:50 +0000) ---------------------------------------------------------------- coresight: Update for v6.2 CoreSight updatesfor v6.2 includes : - Support for ETMv4 probing on hotplugged CPUs - Fix TRBE driver for cpuhp state refcounting - Fix CTI driver NULL pointer dereferencing - Fix comment for repeated word Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Jilin Yuan (1): coresight: etm4x: fix repeated words in comments Mike Leach (1): coresight: cti: Fix null pointer error on CTI init before ETM Tamas Zsoldos (1): coresight: etm4x: add CPU hotplug support for probing Yang Shen (1): coresight: trbe: remove cpuhp instance node before remove cpuhp state drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 155 +++++++++++++++------ drivers/hwtracing/coresight/coresight-trbe.c | 1 + 3 files changed, 116 insertions(+), 42 deletions(-)

1 year, 11 months

[PATCH] coresight: cti: Fix null pointer error on CTI init before ETM

by Mike Leach

When CTI is discovered first then the function coresight_set_assoc_ectdev_mutex() is called to set the association between CTI and ETM device. Recent lockdep fix passes a null pointer. This patch passes the correct pointer. Before patch: log of boot oops sequence with CTI discovered first: [ 12.424091] cs_system_cfg: CoreSight Configuration manager initialised [ 12.483474] coresight cti_sys0: CTI initialized [ 12.488109] coresight cti_sys1: CTI initialized [ 12.503594] coresight cti_cpu0: CTI initialized [ 12.517877] coresight-cpu-debug 850000.debug: Coresight debug-CPU0 initialized [ 12.523479] coresight-cpu-debug 852000.debug: Coresight debug-CPU1 initialized [ 12.529926] coresight-cpu-debug 854000.debug: Coresight debug-CPU2 initialized [ 12.541808] coresight stm0: STM32 initialized [ 12.544421] coresight-cpu-debug 856000.debug: Coresight debug-CPU3 initialized [ 12.585639] coresight cti_cpu1: CTI initialized [ 12.614028] coresight cti_cpu2: CTI initialized [ 12.631679] CSCFG registered etm0 [ 12.633920] coresight etm0: CPU0: etm v4.0 initialized [ 12.656392] coresight cti_cpu3: CTI initialized ... [ 12.708383] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000348 ... [ 12.755094] Internal error: Oops: 0000000096000044 [#1] SMP [ 12.761817] Modules linked in: coresight_etm4x(+) coresight_tmc coresight_cpu_debug coresight_replicator coresight_funnel coresight_cti coresight_tpiu coresight_stm coresight [ 12.767210] CPU: 3 PID: 1346 Comm: systemd-udevd Not tainted 6.1.0-rc3tid-v6tid-v6-235166-gf7f7d7a2204a-dirty #498 [ 12.782827] Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) [ 12.793154] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 12.800010] pc : coresight_set_assoc_ectdev_mutex+0x30/0x50 [coresight] [ 12.806694] lr : coresight_set_assoc_ectdev_mutex+0x30/0x50 [coresight] ... [ 12.885064] Call trace: [ 12.892352] coresight_set_assoc_ectdev_mutex+0x30/0x50 [coresight] [ 12.894693] cti_add_assoc_to_csdev+0x144/0x1b0 [coresight_cti] [ 12.900943] coresight_register+0x2c8/0x320 [coresight] [ 12.906844] etm4_add_coresight_dev.isra.27+0x148/0x280 [coresight_etm4x] [ 12.912056] etm4_probe+0x144/0x1c0 [coresight_etm4x] [ 12.918998] etm4_probe_amba+0x40/0x78 [coresight_etm4x] [ 12.924032] amba_probe+0x11c/0x1f0 After patch: similar log [ 12.444467] cs_system_cfg: CoreSight Configuration manager initialised [ 12.456329] coresight-cpu-debug 850000.debug: Coresight debug-CPU0 initialized [ 12.456754] coresight-cpu-debug 852000.debug: Coresight debug-CPU1 initialized [ 12.469672] coresight-cpu-debug 854000.debug: Coresight debug-CPU2 initialized [ 12.476098] coresight-cpu-debug 856000.debug: Coresight debug-CPU3 initialized [ 12.532409] coresight stm0: STM32 initialized [ 12.533708] coresight cti_sys0: CTI initialized [ 12.539478] coresight cti_sys1: CTI initialized [ 12.550106] coresight cti_cpu0: CTI initialized [ 12.633931] coresight cti_cpu1: CTI initialized [ 12.634664] coresight cti_cpu2: CTI initialized [ 12.638090] coresight cti_cpu3: CTI initialized [ 12.721136] CSCFG registered etm0 ... [ 12.762643] CSCFG registered etm1 [ 12.762666] coresight etm1: CPU1: etm v4.0 initialized [ 12.776258] CSCFG registered etm2 [ 12.776282] coresight etm2: CPU2: etm v4.0 initialized [ 12.784357] CSCFG registered etm3 [ 12.785455] coresight etm3: CPU3: etm v4.0 initialized Error can also be triggered by manually starting the modules using modprobe in the following order: root@linaro-developer:/home/linaro/cs-mods# modprobe coresight root@linaro-developer:/home/linaro/cs-mods# modprobe coresight-cti root@linaro-developer:/home/linaro/cs-mods# modprobe coresight-etm4x Tested on Dragonboard DB410c Applies to coresight/next Fixes: 23722fb46725 ("coresight: Fix possible deadlock with lock dependency") Signed-off-by: Mike Leach <mike.leach(a)linaro.org> --- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index c6e8c6542f24..d2cf4f4848e1 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -564,7 +564,7 @@ static void cti_add_assoc_to_csdev(struct coresight_device *csdev) * if we found a matching csdev then update the ECT * association pointer for the device with this CTI. */ - coresight_set_assoc_ectdev_mutex(csdev->ect_dev, + coresight_set_assoc_ectdev_mutex(csdev, ect_item->csdev); break; } -- 2.17.1

1 year, 11 months

Re: [PATCH] coresight: trbe: remove cpuhp instance node before remove cpuhp state

by Suzuki Kuruppassery Poulose

On 22/11/2022 09:03, Yang Shen wrote: > cpuhp_state_add_instance() and cpuhp_state_remove_instance() should > be used in pairs. Or there will lead to the warn on > cpuhp_remove_multi_state() since the cpuhp_step list is not empty. > > The following is the error log with 'rmmod coresight-trbe': > Error: Removing state 215 which has instances left. > Call trace: > __cpuhp_remove_state_cpuslocked+0x144/0x160 > __cpuhp_remove_state+0xac/0x100 > arm_trbe_device_remove+0x2c/0x60 [coresight_trbe] > platform_remove+0x34/0x70 > device_remove+0x54/0x90 > device_release_driver_internal+0x1e4/0x250 > driver_detach+0x5c/0xb0 > bus_remove_driver+0x64/0xc0 > driver_unregister+0x3c/0x70 > platform_driver_unregister+0x20/0x30 > arm_trbe_exit+0x1c/0x658 [coresight_trbe] > __arm64_sys_delete_module+0x1ac/0x24c > invoke_syscall+0x50/0x120 > el0_svc_common.constprop.0+0x58/0x1a0 > do_el0_svc+0x38/0xd0 > el0_svc+0x2c/0xc0 > el0t_64_sync_handler+0x1ac/0x1b0 > el0t_64_sync+0x19c/0x1a0 > ---[ end trace 0000000000000000 ]--- > > Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") > Signed-off-by: Yang Shen <shenyang39(a)huawei.com> > --- > drivers/hwtracing/coresight/coresight-trbe.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 2b386bb848f8..1fc4fd79a1c6 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -1434,6 +1434,7 @@ static int arm_trbe_probe_cpuhp(struct trbe_drvdata *drvdata) > > static void arm_trbe_remove_cpuhp(struct trbe_drvdata *drvdata) > { > + cpuhp_state_remove_instance(drvdata->trbe_online, &drvdata->hotplug_node); > cpuhp_remove_multi_state(drvdata->trbe_online); > } > Applied to coresight next. https://git.kernel.org/coresight/c/5fefef85b0d3 Thanks Suzuki > -- > 2.24.0 >

1 year, 11 months

[PATCH v13 0/2] Add support for UltraSoc System Memory Buffer

by Junhao He

Add support for UltraSoc System Memory Buffer. Change since v12: - Modify the code style and add "#ifdef CONFIG_ACPI" according to Jonathan's comment. - Address the comments from Yicong. - Link: https://lore.kernel.org/lkml/20221109135008.9485-1-hejunhao3@huawei.com/ Change since v11: - Modify the code style and rename the macro according to Jonathan's comment. - Link: https://lore.kernel.org/lkml/20221107130624.59886-1-hejunhao3@huawei.com/ Change since v10: - Rebase onto v6.1-rc4, included similar sysfs register accessors (as same as James's patch) - Link: https://lore.kernel.org/lkml/20221022115929.7503-1-hejunhao3@huawei.com/ Change since v9: - Update the Contact tag in SMB document. - Replace the spinlock with mutex. - Do some clean-ups in "smb_enable()" and "smb_release()". - Use classic memory mapped interface. - Link: https://lore.kernel.org/linux-arm-kernel/20220818132231.28240-1-hejunhao3@h… Change since v8: - Insert a blank line at the end of the config tag in Kconfig according to Randy's comment. - Link: https://lore.kernel.org/linux-arm-kernel/20220816131634.38195-1-hejunhao3@h… Change since v7: - Use the macros for register bit flags and numbers of resource. - Cleanup punctuation. - Update the Date tag and the KernelVersion tag in the document. - Link: https://lore.kernel.org/lkml/20220712091353.34540-1-hejunhao3@huawei.com/ Change since v6: - Modify the code style and driver description according to Suzuki's comment. - Modify configuration of "drvdata->reading", to void problems in open/read concurrency scenario. - Rename the macro of "SMB_FLOW_MASK". - Use the "handle->head" to determine the page number and offset. - Link: https://lore.kernel.org/linux-arm-kernel/20220606130223.57354-1-liuqi115@hu… Change since v5: - Address the comments from Suzuki, add some comments in SMB document, and modify configuration of "drvdata->reading", to void problems in multi-core concurrency scenario - Link: https://lore.kernel.org/linux-arm-kernel/20220416083953.52610-1-liuqi115@hu… Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - Link: https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link: https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi115@hu… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight by Mathieu's comment. - Link: https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB drivers .../sysfs-bus-coresight-devices-ultra_smb | 31 + .../trace/coresight/ultrasoc-smb.rst | 82 +++ drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 646 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 120 ++++ 6 files changed, 891 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.33.0

1 year, 11 months

[PATCH v5 00/14] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Appies to coresight/next [30a0b95b1335] Changes since v4: 1) update to ensure that compiling after each individual patch added still works - ie. git bisect not broken through the patchset.. 2) Revision to some of the now redundant code in cs-etm (James) 3) Comments and other minor fixes requested by Suzuki. Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (14): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: perf: traceid: Add perf ID allocation and notifiers coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: trace id: Remove legacy get trace ID function. perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +-- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 90 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 70 +++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 258 ++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 154 ++++++++ include/linux/coresight-pmu.h | 34 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 328 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 980 insertions(+), 231 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

1 year, 11 months

[PATCH v1 0/9] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc(a)0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This series applies to coresight/next https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git?h=next This patch series depends on patch series "[v12,0/9] Coresight: Add support for TPDM and TPDA" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221114144027.… Tao Zhang (9): dt-bindings: arm: Add support for DSB element coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb element creation coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request .../bindings/arm/qcom,coresight-tpda.yaml | 9 + drivers/hwtracing/coresight/coresight-tpda.c | 62 ++ drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 630 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 65 +++ 5 files changed, 765 insertions(+), 5 deletions(-) -- 2.7.4

1 year, 11 months

Re: [PATCH v13 2/2] Documentation: Add document for UltraSoc SMB drivers

by hejunhao

Hi Bagas, On 2022/11/15 15:35, Bagas Sanjaya wrote: > On 11/15/22 14:33, hejunhao wrote: >> Hi Bagas, >> >> will apply the fix in next version. >> Thank you very much. >> > Please don't top-post, reply inline with appropriate context instead. > I had to trim all the below context as a result. Yes, I'm sorry for that. Best regards, Junhao.

1 year, 11 months

Re: [PATCH v13 0/2] Add support for UltraSoc System Memory Buffer

by hejunhao

Hi Bagas, On 2022/11/14 21:11, Bagas Sanjaya wrote: > On Mon, Nov 14, 2022 at 05:03:14PM +0800, Junhao He wrote: >> Add support for UltraSoc System Memory Buffer. >> > The cover letter message (aside changelogs) is short but LGTM. However, > for individual patches description, please write in imperative mood > (that is, no "This patch/commit does foo" but "Do foo" instead). > > Thanks. Yes, I will do that. Best regards, Junhao.

1 year, 11 months

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