Re: [PATCH v1 RESEND 2/3] coresight-tpdm: Add support to select lane

On 11/10/2024 07:47, Mao Jinlong wrote:

From: Tao Zhang quic_taozha@quicinc.com

TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB configurations, the field "XTRIG_LNSEL" in CMB_CR register selects which lane participates in the output pattern mach cross trigger mechanism goverened by the M_CMB_DXPR and M_CMB_XPMR regisers.

minor nit: s/goverened/governed/

Signed-off-by: Tao Zhang quic_taozha@quicinc.com

.../testing/sysfs-bus-coresight-devices-tpdm | 8 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 51 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 62 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index bf710ea6e0ef..b3292fa2a022 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -257,3 +257,11 @@ Contact: Jinlong Mao (QUIC) quic_jinlmao@quicinc.com, Tao Zhang (QUIC) <quic_t Description: (RW) Set/Get the MSR(mux select register) for the CMB subunit TPDM.

+What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane +Date: June 2024 +KernelVersion 6.9 +Contact: Tao Zhang (QUIC) quic_taozha@quicinc.com

Didn't we already discuss about modifying the date and version ? Simply resending the patch is not going to help if it is not uptodate.

Please fix all the dates in the series

Suzuki

+Description:

• (RW) Set/Get which lane participates in the output pattern
  

• match cross trigger mechanism for the MCMB subunit TPDM.
  

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 58f8c3e804c1..f32c119e1b67 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -238,6 +238,18 @@ static umode_t tpdm_cmb_msr_is_visible(struct kobject *kobj, return 0; } +static umode_t tpdm_mcmb_is_visible(struct kobject *kobj,

• 		    struct attribute *attr, int n)
  

+{

• struct device *dev = kobj_to_dev(kobj);
• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• if (drvdata && tpdm_has_mcmb_dataset(drvdata))

• return attr->mode;
  

• return 0;

+}

• static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) {

@@ -1015,6 +1027,34 @@ static ssize_t cmb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_trig_ts); +static ssize_t mcmb_trig_lane_show(struct device *dev,

• 		   struct device_attribute *attr,
  

• 		   char *buf)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• return sysfs_emit(buf, "%u\n",

• 	  (unsigned int)drvdata->cmb->mcmb->mcmb_trig_lane);
  

+}

+static ssize_t mcmb_trig_lane_store(struct device *dev,

• 		    struct device_attribute *attr,
  

• 		    const char *buf,
  

• 		    size_t size)
  

+{

• struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
• unsigned long val;
• if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_MCMB_MAX_LANES))

• return -EINVAL;
  

• guard(spinlock)(&drvdata->spinlock);
• drvdata->cmb->mcmb->mcmb_trig_lane = val;
• return size;

+} +static DEVICE_ATTR_RW(mcmb_trig_lane);

• static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr,

@@ -1177,6 +1217,11 @@ static struct attribute *tpdm_cmb_msr_attrs[] = { NULL, }; +static struct attribute *tpdm_mcmb_attrs[] = {

• &dev_attr_mcmb_trig_lane.attr,
• NULL,

+};

• static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr,

@@ -1243,6 +1288,11 @@ static struct attribute_group tpdm_cmb_msr_grp = { .name = "cmb_msr", }; +static struct attribute_group tpdm_mcmb_attr_grp = {

• .attrs = tpdm_mcmb_attrs,
• .is_visible = tpdm_mcmb_is_visible,

+};

• static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp,

@@ -1254,6 +1304,7 @@ static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_cmb_trig_patt_grp, &tpdm_cmb_patt_grp, &tpdm_cmb_msr_grp,

• &tpdm_mcmb_attr_grp, NULL, };

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 2e84daad1a58..e72dc19da310 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -45,6 +45,9 @@ /* MAX number of DSB MSR */ #define TPDM_CMB_MAX_MSR 32 +/* MAX lanes in the output pattern for MCMB configurations*/ +#define TPDM_MCMB_MAX_LANES 8

• /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784)