On 07/01/2022 01:10, Anshuman Khandual wrote:
TRBE implementations affected by Arm erratum #2038923 might get TRBE into an inconsistent view on whether trace is prohibited within the CPU. As a result, the trace buffer or trace buffer state might be corrupted. This happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, followed by just a single context synchronization event before execution changes from a context, in which trace is prohibited to one where it isn't, or vice versa. In these mentioned conditions, the view of whether trace is prohibited is inconsistent between parts of the CPU, and the trace buffer or the trace buffer state might be corrupted.
Work around this problem in the TRBE driver by preventing an inconsistent view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or two ISB instructions if no ERET is to take place. This just updates the TRBE driver as required.
Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Suzuki Poulose suzuki.poulose@arm.com Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
arch/arm64/Kconfig | 2 +- drivers/hwtracing/coresight/coresight-trbe.c | 48 +++++++++++++++----- 2 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b6d62672bf7d..209e481acf0d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -798,7 +798,7 @@ config ARM64_ERRATUM_2064142 config ARM64_ERRATUM_2038923 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
- depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
- depends on CORESIGHT_TRBE default y help This option adds the workaround for ARM Cortex-A510 erratum 2038923.
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 850e9fca6847..c4cc529749f8 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -92,11 +92,13 @@ struct trbe_buf { #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 +#define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 static int trbe_errata_cpucaps[] = { [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142,
- [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, -1, /* Sentinel, must be the last entry */ };
@@ -174,6 +176,11 @@ static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); } +static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudata) +{
- return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE);
+}
- static int trbe_alloc_node(struct perf_event *event) { if (event->cpu == -1)
@@ -187,6 +194,28 @@ static inline void trbe_drain_buffer(void) dsb(nsh); } +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) +{
- /*
* Enable the TRBE without clearing LIMITPTR which* might be required for fetching the buffer limits.*/- trblimitr |= TRBLIMITR_ENABLE;
- write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1);
- /* Synchronize the TRBE enable event */
- isb();
- /*
* Errata affected TRBE implementation will need an additional* context synchronization in order to prevent an inconsistent* TRBE prohibited region view on the CPU which could possibly* corrupt the TRBE buffer or the TRBE state.*/- if (trbe_needs_ctxt_sync_after_enable(cpudata))
isb();+}
Similar to the previous patch, we may move the comment to the function where it is defined.
Either ways:
Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com