TPDM CMB subunits support two forms of CMB data set element creation: continuous and trace-on-change collection mode. Continuous change creates CMB data set elements on every CMBCLK edge. Trace-on-change creates CMB data set elements only when a new data set element differs in value from the previous element in a CMB data set. Set CMB_CR.MODE to 0 for continuous CMB collection mode. Set CMB_CR.MODE to 1 for trace-on-change CMB collection mode
Signed-off-by: Mao Jinlong quic_jinlmao@quicinc.com --- .../testing/sysfs-bus-coresight-devices-tpdm | 8 ++ drivers/hwtracing/coresight/coresight-tpdm.c | 77 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 12 +++ 3 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 6bdba7d375c9..89051018dd70 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -155,3 +155,11 @@ Description: Accepts the following two values. value 1: Index number of MSR register value 2: The value need to be written + +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode +Date: March 2023 +KernelVersion 6.3 +Contact: Jinlong Mao quic_jinlmao@quicinc.com +Description: (RW) Read or write CMB data collection mode. Only value 0 and 1 can be written to this node. + Set to 0 is for continuous CMB collection mode. Set to 1 is for trace-on-change CMB + collection mode. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index d92432329c9c..68244abfc8b9 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -34,6 +34,21 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj, return 0; }
+static umode_t tpdm_cmb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (drvdata) { + if (drvdata->datasets & TPDM_PIDR0_DS_CMB) + return attr->mode; + } + + return 0; +} + + static int tpdm_init_datasets(struct tpdm_drvdata *drvdata) { if (drvdata->datasets & TPDM_PIDR0_DS_DSB) { @@ -50,6 +65,15 @@ static int tpdm_init_datasets(struct tpdm_drvdata *drvdata) &drvdata->dsb->msr_num); }
+ if (drvdata->datasets & TPDM_PIDR0_DS_CMB) { + if (!drvdata->cmb) { + drvdata->cmb = devm_kzalloc(drvdata->dev, + sizeof(*drvdata->cmb), GFP_KERNEL); + if (!drvdata->cmb) + return -ENOMEM; + } + } + return 0; }
@@ -154,9 +178,18 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) u32 val;
val = readl_relaxed(drvdata->base + TPDM_CMB_CR); - val |= TPDM_CMB_CR_ENA; + /* + * Set to 0 for continuous CMB collection mode, + * 1 for trace-on-change CMB collection mode. + */ + if (drvdata->cmb->trace_mode) + val |= TPDM_CMB_CR_MODE; + else + val &= ~TPDM_CMB_CR_MODE;
/* Set the enable bit of CMB control register to 1 */ + val |= TPDM_CMB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); }
@@ -819,6 +852,37 @@ static ssize_t dsb_msr_store(struct device *dev, } static DEVICE_ATTR_RW(dsb_msr);
+static ssize_t cmb_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%x\n", + drvdata->cmb->trace_mode); + +} + +static ssize_t cmb_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long trace_mode; + int ret; + + ret = kstrtoul(buf, 16, &trace_mode); + if (ret || (trace_mode & ~1UL)) + return -EINVAL; + + spin_lock(&drvdata->spinlock); + drvdata->cmb->trace_mode = trace_mode; + spin_unlock(&drvdata->spinlock); + return size; +} +static DEVICE_ATTR_RW(cmb_mode); + static struct attribute *tpdm_dsb_attrs[] = { &dev_attr_dsb_mode.attr, &dev_attr_dsb_edge_ctrl.attr, @@ -835,14 +899,25 @@ static struct attribute *tpdm_dsb_attrs[] = { NULL, };
+static struct attribute *tpdm_cmb_attrs[] = { + &dev_attr_cmb_mode.attr, + NULL, +}; + static struct attribute_group tpdm_dsb_attr_grp = { .attrs = tpdm_dsb_attrs, .is_visible = tpdm_dsb_is_visible, };
+static struct attribute_group tpdm_cmb_attr_grp = { + .attrs = tpdm_cmb_attrs, + .is_visible = tpdm_cmb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] = { &tpdm_attr_grp, &tpdm_dsb_attr_grp, + &tpdm_cmb_attr_grp, NULL, };
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4c065a4b8a75..d716963bee10 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -15,6 +15,8 @@
/* Enable bit for CMB subunit */ #define TPDM_CMB_CR_ENA BIT(0) +/* Trace collection mode for CMB subunit*/ +#define TPDM_CMB_CR_MODE BIT(1)
/* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) @@ -117,6 +119,14 @@ struct dsb_dataset { u32 *msr; };
+/* + * struct cmb_dataset + * @trace_mode: Dataset collection mode + */ +struct cmb_dataset { + u32 trace_mode; +}; + /** * struct tpdm_drvdata - specifics associated to an TPDM component * @base: memory mapped base address for this component. @@ -125,6 +135,7 @@ struct dsb_dataset { * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @datasets: The datasets types present of the TPDM. + * @cmb: cmb dataset struct data. */
struct tpdm_drvdata { @@ -135,6 +146,7 @@ struct tpdm_drvdata { bool enable; unsigned long datasets; struct dsb_dataset *dsb; + struct cmb_dataset *cmb; };
#endif /* _CORESIGHT_CORESIGHT_TPDM_H */