Re: [PATCH v3 19/31] coresight: cti: Introduce CS_MODE_DEBUG mode

Hi,

On Mon, 15 Sept 2025 at 11:34, Leo Yan leo.yan@arm.com wrote:

Introduce a new CS_MODE_DEBUG mode to indicate that a device is being used for debugging purposes, e.g, if a system enables CTI for debugging but not for hardware trace

How can you know why the CTI is being enabled?

System CTIs are attached to key HW trace infrastucture such as input triggers for ETR/ETB that have direct effect on trace. CoreCTIs, while they have some debug triggers, can also trigger ETM events.

Mike

Update ETM4x driver to mute compiler warnings for the newly added mode.

Signed-off-by: Leo Yan leo.yan@arm.com

drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ include/linux/coresight.h | 9 +++++---- 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 572b80ee96fbf18ec8cf9abc30d109a676dfbc5d..3e0039f75f5aad104cb86561bf37971c7dc4e408 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -112,7 +112,7 @@ static ssize_t enable_store(struct device *dev, ret = pm_runtime_resume_and_get(dev->parent); if (ret) return ret;

•           ret = cti_enable(drvdata->csdev, CS_MODE_SYSFS, NULL);
  

•           ret = cti_enable(drvdata->csdev, CS_MODE_DEBUG, NULL);
            if (ret)
                    pm_runtime_put(dev->parent);
    } else {
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b63433e80d305588c18b084408496690480a7af0..4218cefca63d7b2f3b102e74d7f007ebc7b08861 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -934,6 +934,7 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, case CS_MODE_PERF: ret = etm4_enable_perf(csdev, event, path); break;

•   case CS_MODE_DEBUG:
    default:
            ret = -EINVAL;
    }
  

@@ -1132,6 +1133,7 @@ static void etm4_disable(struct coresight_device *csdev, mode = coresight_get_mode(csdev);

    switch (mode) {

•   case CS_MODE_DEBUG:
    case CS_MODE_DISABLED:
            break;
    case CS_MODE_SYSFS:
  

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 39781ba24ee2ad9f3065770409aafb0e5af57fa8..462876b5a870f3e93ad2a1807a9045d5eb115ccd 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -253,10 +253,10 @@ struct coresight_trace_id_map {

•         by @coresight_ops.
  

• @access: Device i/o access abstraction for this device.
• @dev: The device entity associated to this component.

• • @mode: The device mode, i.e sysFS, Perf or disabled. This is actually

• •         an 'enum cs_mode' but stored in an atomic type. Access is always
    

• •         through atomic APIs, ensuring SMP-safe synchronisation between
    

• •         racing from sysFS and Perf mode. A compare-and-exchange
    

• • @mode: The device mode, i.e sysFS, Perf, debug or disabled. This is

• •         actually an 'enum cs_mode' but stored in an atomic type. Access
    

• •         is always through atomic APIs, ensuring SMP-safe synchronisation
    

• •         between racing from sysFS and Perf mode. A compare-and-exchange
    

  •         operation is done to atomically claim one mode or the other.
    

  • @refcnt: keep track of what is in use. Only access this outside of the

  •         device's spinlock when the coresight_mutex held and mode ==
    

@@ -344,6 +344,7 @@ enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS, CS_MODE_PERF,

•   CS_MODE_DEBUG,
  

};

#define coresight_ops(csdev) csdev->ops

-- 2.34.1