Hi,
-----Original Message----- From: CoreSight [mailto:coresight-bounces@lists.linaro.org] On Behalf Of Kim Phillips Sent: 09 February 2018 03:20 To: Christian Hansen (chansen3) chansen3@cisco.com; coresight@lists.linaro.org Cc: linux-perf-users@vger.kernel.org Subject: Re: Recording memory addresses on ARM
On Thu, 8 Feb 2018 15:17:33 +0000 "Christian Hansen (chansen3)" chansen3@cisco.com wrote:
Is is possible to capture the address of memory accesses using perf on ARM? Initially, I thought perf-mem would do the trick, but apparently its functionality is entirely dependent on Intel CPUs with PEBS.
Right.
Then I noticed that perf-record takes a -d flag (used by perf-mem). Although the description of that flag is vague (capture what addresses? ), when used as such "perf record -e armv8_cortex_a72/mem_access/u -d -p 16963 sleep 5” and then dumping the trace via “perf report — mem-mode” I get 0s in the data symbol column. So this also appears to have no effect on my hardware. As the command used reveals, I’m using perf on a Cortex A72 and on Linux 4.4.
I see ./perf report --help says:
--mem-mode Use the data addresses of samples in addition to instruction addressesto build the histograms. To generate meaningful output, the perf.data file must have been obtained using perf record -d -W and using a special event -e cpu/mem-loads/ or -e cpu/mem-stores/. See perf mem for simpler access.
yet perf record's -W switch isn't on record's manpage, and trying the invocation sequence on x86 using a perf built from today's acme's perf/urgent branch:
$ ./perf version perf version 4.13.rc5.g59410f5 $ ./perf record -e cpu/mem-loads/u -d -W -p 3722 sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 8.978 MB perf.data ] $ ./perf report --mem-mode --stdio Error: The perf.data file has no samples! # To display the perf.data header info, please use --header/--header-only options. # $
A 'perf mem record sleep 1; perf mem report' sequence produces samples in its output, but 'mem record' doesn't take a -p switch for the PID, rather, -p means --phys-data, "Record/Report sample physical addresses", which also doesn't seem to work:
$ perf mem -p record sleep 1 Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (cpu/mem-loads,ldlat=30/P). /bin/dmesg may provide additional information. No CONFIG_PERF_EVENTS=y kernel support configured?
Nevertheless, on Arm, the armv8_cortex_a72/mem_access/ is a counting PMU, so it doesn't record the address of the memory access, just where in the code the access came from.
I’m aware that for ARM there’s a Statistical Profiling Extension for which support went into the kernel recently and which could potentially support this information, but that requires ARMv8.2. There’s an
Ack.
Embedded Trace Macrocell on my CPU and perf support is also in the kernel, but my understanding is that capturing a data trace is not available for A profile CPUs, which is what I have.
No, Cortex-As should be supported by the Coresight driver no problem. Try acme's perf/core tree, where support for linking with decode
Am I overlooking some software support for this in perf or am I simply
asking the impossible?
You're on the right track: Coresight trace h/w is able to record memory accesses, but I don't know its enablement status, so I'm adding the coresight mailing list to cc in case anyone there can chime in and help.
Cortex A class cores have, by architectural design*, instruction trace only. This means that while the instructions that access memory are traced as part of the instruction stream, without data trace, data addresses and values are not.
Data trace is an option for R and M class cores.
Regards
Mike
*ARM ETM Spec ETMv4.0 - ETMv4.3; Section 1.3.4 - functional configurations of ETMv4 trace unit.
(as an aside - early v7 A class cores e.g. A8, used ETMv3.x so some did in fact have data trace as an option at hardware SoC design time. However, later variants e.g. A9, moved to PTM - no data trace option at all - or ETMv4 - as above data trace only for R and M)
Thanks,
Kim _______________________________________________ CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
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