On Wed, Oct 28, 2020 at 10:09:42PM +0000, Suzuki K Poulose wrote:
ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available.
Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com
.../coresight/coresight-etm4x-core.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4bc2f15b6332..dc537b5612eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -675,6 +675,37 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static inline bool cpu_supports_sysreg_trace(void) +{
- u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
- return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
I would do:
return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) == 1;
Because any other value than '1' are reserved.
+}
+static bool etm_init_sysreg_access(struct etmv4_drvdata *drvdata,
struct csdev_access *csa)+{
- u32 devarch;
- if (!cpu_supports_sysreg_trace())
return false;- /*
* ETMs implementing sysreg access must implement TRCDEVARCH.*/- devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
- if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
return false;- *csa = (struct csdev_access) {
.io_mem = false,.read = etm4x_sysreg_read,.write = etm4x_sysreg_write,- };
- drvdata->arch = etm_devarch_to_arch(devarch);
- return true;
+}
static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { @@ -705,9 +736,17 @@ static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata, static bool etm_init_csdev_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) {
- /*
* Always choose the memory mapped io, if there is* a memory map to prevent sysreg access on broken* systems.*/
- if (etm_init_sysreg_access(drvdata, csa))
return true;- return false;
With the above:
Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
} -- 2.24.1