On 11/10/2024 07:47, Mao Jinlong wrote:
From: Tao Zhang quic_taozha@quicinc.com
Add the sysfs file to set/get the enablement of the lane. For MCMB configurations, the field "E_LN" in CMB_CR register is the individual lane enables. MCMB lane N is enabled for trace generation when M_CMB_CR.E=1 and M_CMB_CR.E_LN[N]=1. For lanes that are not implemented on a given MCMB configuration, the corresponding bits of this field read as 0 and ignore writes.
Signed-off-by: Tao Zhang quic_taozha@quicinc.com
.../testing/sysfs-bus-coresight-devices-tpdm | 7 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 29 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 39 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index b3292fa2a022..214f681a68ec 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -265,3 +265,10 @@ Contact: Tao Zhang (QUIC) quic_taozha@quicinc.com Description: (RW) Set/Get which lane participates in the output pattern match cross trigger mechanism for the MCMB subunit TPDM.
+What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select +Date: June 2024 +KernelVersion 6.9 +Contact: Tao Zhang (QUIC) quic_taozha@quicinc.com +Description:
(RW) Set/Get the enablement of the individual lane.\ No newline at end of file diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index f32c119e1b67..f8e22f4c3b52 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1055,6 +1055,34 @@ static ssize_t mcmb_trig_lane_store(struct device *dev, } static DEVICE_ATTR_RW(mcmb_trig_lane); +static ssize_t mcmb_lanes_select_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- return sysfs_emit(buf, "%u\n",
(unsigned int)drvdata->cmb->mcmb->mcmb_lane_select);+}
+static ssize_t mcmb_lanes_select_store(struct device *dev,
struct device_attribute *attr,const char *buf,size_t size)+{
- struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
- unsigned long val;
- if (kstrtoul(buf, 0, &val))
if (kstrstoul(buf, 0, &val) || (val & ~TPDM_MCMB_E_LN_MASK)) ?
return -EINVAL;- guard(spinlock)(&drvdata->spinlock);
- drvdata->cmb->mcmb->mcmb_lane_select = val & TPDM_MCMB_E_LN_MASK;
- return size;
+} +static DEVICE_ATTR_RW(mcmb_lanes_select);
- static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr,
@@ -1219,6 +1247,7 @@ static struct attribute *tpdm_cmb_msr_attrs[] = { static struct attribute *tpdm_mcmb_attrs[] = { &dev_attr_mcmb_trig_lane.attr,
- &dev_attr_mcmb_lanes_select.attr, NULL, };
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index e72dc19da310..e740039cd650 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -48,6 +48,9 @@ /* MAX lanes in the output pattern for MCMB configurations*/ #define TPDM_MCMB_MAX_LANES 8 +/* High performance mode */
This doesn't match the descriptions ?
Suzuki
+#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0)
- /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784)