On Thu, Feb 03, 2022 at 12:06:03PM +0000, James Clark wrote:
This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11.
Signed-off-by: James Clark james.clark@arm.com
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +++++++++ 2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index a0cdd2cd978a..c876a63fa84d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1728,8 +1728,11 @@ static ssize_t res_ctrl_store(struct device *dev, /* For odd idx pair inversal bit is RES0 */ if (idx % 2 != 0) /* PAIRINV, bit[21] */
val &= ~BIT(21);- config->res_ctrl[idx] = val & GENMASK(21, 0);
val &= ~TRCRSCTLRn_PAIRINV;- config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV |
TRCRSCTLRn_INV |(TRCRSCTLRn_GROUP_MASK << TRCRSCTLRn_GROUP_SHIFT) |(TRCRSCTLRn_SELECT_MASK << TRCRSCTLRn_SELECT_SHIFT));} diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4d943faade33..dd2156a5e70b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -258,6 +258,15 @@ #define TRCBBCTLR_RANGE_SHIFT 0 #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) +#define TRCRSCTLRn_PAIRINV BIT(21) +#define TRCRSCTLRn_INV BIT(20) +#define TRCRSCTLRn_GROUP_SHIFT 16 +#define TRCRSCTLRn_GROUP_MASK GENMASK(3, 0) +#define TRCRSCTLRn_SELECT_SHIFT 0 +#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
Two extra newlines.
With the above and for patches 02 to 15:
Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
/*
- System instructions to access ETM registers.
- See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
-- 2.28.0