On 6/30/2025 7:08 PM, Leo Yan wrote:
On Mon, Jun 30, 2025 at 06:40:53PM +0800, Yuanfang Zhang wrote:
[...]
The current implementation uses a fixed timeout via coresight_timeout(), which may be insufficient when multiple sources are enabled or under heavy load, leading to TMC readiness or flush completion timeout.
I would suggest that we first make clear if this is a hardware quirk or a common issue in Arm CoreSight.
sure, now this issue has been found that not only CPU ETM, but also subsystem ETM.
As the commit log states, "sources are enabled or under heavy load, leading to TMC readiness or flush completion timeout." I would like to confirm how this situation can happen.
Enable all etms, then cat TMC without disable source.
When disabling a CoreSight path, the driver follows a sequential order: the source device is disabled first, followed by flushing and disabling the TMC. We expect that there should be no contention between source devices and the sink when disabling the path. For a subsystem ETM, I expect we should also follow this sequence.
Leo
this issue is a different case: running cat tmc directly did not disable source.