Re: [PATCH 01/19] coresight: Introduce device access abstraction

Reviewed-by: Mike Leach mike.leach@linaro.org

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

We are about to introduce support for sysreg access to ETMv4.4+ component. Since there are generic routines that access the registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) and in order to preserve the logic of these operations at a single place we introduce an abstraction layer for the accesses to a given device.

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-cti.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + drivers/hwtracing/coresight/coresight-etm3x.c | 1 + drivers/hwtracing/coresight/coresight-etm4x.c | 1 + .../hwtracing/coresight/coresight-funnel.c | 1 + .../coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-tmc.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + drivers/hwtracing/coresight/coresight.c | 49 +++++ include/linux/coresight.h | 197 ++++++++++++++++++ 12 files changed, 256 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 1801804a7762..90da0b842717 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -551,6 +551,7 @@ static int catu_probe(struct amba_device *adev, const struct amba_id *id) dev->platform_data = pdata;

    drvdata->base = base;

•   catu_desc.access = CSDEV_ACCESS_IOMEM(base);
    catu_desc.pdata = pdata;
    catu_desc.dev = dev;
    catu_desc.groups = catu_groups;
  

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 47f3c9abae30..e13e24e4a858 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -849,6 +849,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   cti_desc.access = CSDEV_ACCESS_IOMEM(base);
  
    dev_set_drvdata(dev, drvdata);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 03e3f2590191..42fe174a68f0 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -755,6 +755,7 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index bf22dcfd3327..e3724d8adecb 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -805,6 +805,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 00c9f0bb8b1a..466e6f304751 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1488,6 +1488,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 900690a9f7f0..e8e233cbc130 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -242,6 +242,7 @@ static int funnel_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = coresight_funnel_groups;

•           desc.access = CSDEV_ACCESS_IOMEM(base);
    }
  
    dev_set_drvdata(dev, drvdata);
  

diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 78acf29c49ca..8ba9cbe1d108 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -254,6 +254,7 @@ static int replicator_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = replicator_groups;

•           desc.access = CSDEV_ACCESS_IOMEM(base);
    }
  
    if (fwnode_property_present(dev_fwnode(dev),
  

diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 2ba819a47cf6..fbf86f31f2ab 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -884,6 +884,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    ret = stm_get_stimulus_area(dev, &ch_res);
    if (ret)
  

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 7040d583bed9..5711e55c310c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -458,6 +458,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) }

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index f8583e4032a6..4eb3f50618b6 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -149,6 +149,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    /* Disable tpiu to support older devices */
    tpiu_disable_hw(drvdata);
  

diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e9c90f2de34a..38e9c03ab754 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1387,6 +1387,54 @@ static int __init coresight_init(void) } postcore_initcall(coresight_init);

+u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_relaxed_read32(&csdev->access, offset);
  

+}

+u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_read32(&csdev->access, offset);
  

+}

+void coresight_relaxed_write32(struct coresight_device *csdev,

•                          u32 val,
  

•                          u32 offset)
  

+{

•   csdev_access_relaxed_write32(&csdev->access, val, offset);
  

+}

+void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{

•   csdev_access_write32(&csdev->access, val, offset);
  

+}

+u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_relaxed_read64(&csdev->access, offset);
  

+}

+u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_read64(&csdev->access, offset);
  

+}

+void coresight_relaxed_write64(struct coresight_device *csdev,

•                          u64 val,
  

•                          u32 offset)
  

+{

•   csdev_access_relaxed_write64(&csdev->access, val, offset);
  

+}

+void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{

•   csdev_access_write64(&csdev->access, val, offset);
  

+}

/*

• coresight_release_platform_data: Release references to the devices connected
• to the output port of this device.

@@ -1451,6 +1499,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) csdev->type = desc->type; csdev->subtype = desc->subtype; csdev->ops = desc->ops;

•   csdev->access = desc->access;
    csdev->orphan = false;
  
    csdev->dev.type = &coresight_dev_type[desc->type];
  

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 58fffdecdbfd..1377240275d8 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -7,6 +7,7 @@ #define _LINUX_CORESIGHT_H

#include <linux/device.h> +#include <linux/io.h> #include <linux/perf_event.h> #include <linux/sched.h>

@@ -114,6 +115,38 @@ struct coresight_platform_data { struct coresight_connection *conns; };

+/**

• • struct csdev_access - Abstraction of a CoreSight device access.
• • @io_mem : True if the device has memory mapped I/O
• • @base : When io_mem == true, base address of the component
• • @read : Read from the given "offset" of the given instance.
• • @write : Write "val" to the given "offset".
• */

+struct csdev_access {

•   bool io_mem;
  

•   union {
  

•           void __iomem *base;
  

•           struct {
  

•                   u64 (*read)(struct csdev_access *csa,
  

•                               u32 offset,
  

•                               bool relaxed,
  

•                               bool _64bit);
  

•                   void (*write)(struct csdev_access *csa,
  

•                                 u64 val,
  

•                                 u32 offset,
  

•                                 bool relaxed,
  

•                                 bool _64bit);
  

•           };
  

•   };
  

+};

+#define CSDEV_ACCESS_IOMEM(addr) \

•   (struct csdev_access)   {               \
  

•           .io_mem         = true,         \
  

•           .base           = addr,         \
  

•   }
  

/**

• struct coresight_desc - description of a component required from drivers
• @type: as defined by @coresight_dev_type.

@@ -125,6 +158,7 @@ struct coresight_platform_data {

• @groups: operations specific to this component. These will end up

•         in the component's sysfs sub-directory.
  

• @name: name for the coresight device, also shown under sysfs.

• • @access: Describe access to the device
  */

struct coresight_desc { enum coresight_dev_type type; @@ -134,6 +168,7 @@ struct coresight_desc { struct device *dev; const struct attribute_group **groups; const char *name;

•   struct csdev_access access;
  

};

/** @@ -186,6 +221,7 @@ struct coresight_sysfs_link {

• @def_sink: cached reference to default sink found for this device.
• @ect_dev: Associated cross trigger device. Not part of the trace data

•         path or connections.
  

• • @access: Device i/o access abstraction for this device.
  • @nr_links: number of sysfs links created to other components from this

  •         device. These will appear in the "connections" group.
    

  • @has_conns_grp: Have added a "connections" group for sysfs links.

@@ -205,6 +241,7 @@ struct coresight_device { struct coresight_device *def_sink; /* cross trigger handling */ struct coresight_device *ect_dev;

•   struct csdev_access access;
    /* sysfs links between components */
    int nr_links;
    bool has_conns_grp;
  

@@ -324,6 +361,107 @@ struct coresight_ops { const struct coresight_ops_ect *ect_ops; };

+static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,

•                                         u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           return readl_relaxed(csa->base + offset);
  

•   return csa->read(csa, offset, true, false);
  

+}

+static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           return readl(csa->base + offset);
  

•   return csa->read(csa, offset, false, false);
  

+}

+static inline void csdev_access_relaxed_write32(struct csdev_access *csa,

•                                           u32 val,
  

•                                           u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           writel_relaxed(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, true, false);
  

+}

+static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           writel(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, false, false);
  

+}

+#ifdef CONFIG_64BIT

+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,

•                                      u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           return readq_relaxed(csa->base + offset);
  

•   return csa->read(csa, offset, true, true);
  

+}

+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           return readq(csa->base + offset);
  

•   return csa->read(csa, offset, false, true);
  

+}

+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,

•                                           u64 val,
  

•                                           u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           writeq_relaxed(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, true, true);
  

+}

+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           writeq(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, false, true);
  

+}

+#else

+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,

•                                      u32 offset)
  

+{

•   WARN_ON(1);
  

•   return 0;
  

+}

+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{

•   WARN_ON(1);
  

•   return 0;
  

+}

+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,

•                                           u64 val,
  

•                                           u32 offset)
  

+{

•   WARN_ON(1);
  

+}

+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{

•   WARN_ON(1);
  

+} +#endif

#ifdef CONFIG_CORESIGHT extern struct coresight_device * coresight_register(struct coresight_desc *desc); @@ -342,6 +480,20 @@ extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev);

extern bool coresight_loses_context_with_cpu(struct device *dev);

+u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); +u32 coresight_read32(struct coresight_device *csdev, u32 offset); +void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); +void coresight_relaxed_write32(struct coresight_device *csdev,

•                          u32 val,
  

•                          u32 offset);
  

+u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); +u64 coresight_read64(struct coresight_device *csdev, u32 offset); +void coresight_relaxed_write64(struct coresight_device *csdev,

•                          u64 val, u32 offset);
  

+void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);

#else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } @@ -368,6 +520,51 @@ static inline bool coresight_loses_context_with_cpu(struct device *dev) { return false; }

+static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{ +}

+static inline void coresight_relaxed_write32(struct coresight_device *csdev,

•                                         u32 val, u32 offset);
  

+{ +}

+static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,

•                                      u32 offset)
  

+{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline void coresight_relaxed_write64(struct coresight_device *csdev,

•                                        u64 val,
  

•                                        u32 offset)
  

+{ +}

+static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{ +}

#endif

extern int coresight_get_cpu(struct device *dev);

2.24.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK