On Mon, Jan 4, 2021 at 11:15 AM Mathieu Poirier mathieu.poirier@linaro.org wrote:
On Mon, Jan 04, 2021 at 02:42:08PM +0000, Suzuki K Poulose wrote:
Hi Rob,
On 1/3/21 5:02 PM, Rob Herring wrote:
On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose suzuki.poulose@arm.com
Document the device tree bindings for Embedded Trace Extensions. ETE can be connected to legacy coresight components and thus could optionally contain a connection graph as described by the CoreSight bindings.
Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Cc: Rob Herring robh@kernel.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com
Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ete.txt
Bindings are in schema format now, please convert this.
Sure, will do that.
diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt new file mode 100644 index 0000000..b52b507 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ete.txt @@ -0,0 +1,41 @@ +Arm Embedded Trace Extensions
+Arm Embedded Trace Extensions (ETE) is a per CPU trace component that +allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 +architecture and has extended support for future architecture changes. +The trace generated by the ETE could be stored via legacy CoreSight +components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer +Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to +legacy CoreSight components, a node must be listed per instance, along +with any optional connection graph as per the coresight bindings. +See bindings/arm/coresight.txt.
+** ETE Required properties:
+- compatible : should be one of:
- "arm,embedded-trace-extensions"
+- cpu : the CPU phandle this ETE belongs to.
If this is 1:1 with CPUs, then perhaps it should be a child node of the CPU nodes.
Yes, it is 1:1 with the CPUs. I have tried to keep this aligned with that of "coresight-etm4x". The same driver handles both. The only reason why this was separated from the "coresight.txt" is to describe the new configurations possible (read, TRBE).
Would it be possible to keep the CPU handle rather than moving things under the CPU nodes? ETMv3.x and ETMv4.x are using a handle and as Suzuki points out ETE and ETMv4.x are sharing the same driver. Proceeding differently for the ETE would be terribly confusing.
Yeah, no problem.
Rob