Hi, Mike
Thanks for your answer!
On Wed, Jan 27, 2016 at 8:16 PM, Mike Leach Mike.Leach@arm.com wrote:
Hi Chunyan,
A quick follow up to this after a discussion with one of the trace architects. The STM drives the trace ATB interface at the main STM clock speed (the CLK input). It is up to the system designer to choose when they bridge from the CLK to the ATCLK for input to ATCLKed trace components.
The system designer, you meant the hardware system designer?
So is the ATCLK a hardware stuff? As a software programmer, do I need to deal with ATCLK in drivers (including STM's and other components' drivers)?
Thanks, Chunyan
Regards
Mike
Mike Leach +44 (0)1254 893911 (Direct) Principal Engineer +44 (0)1254 893900 (Main) Arm Blackburn Design Centre +44 (0)1254 893901 (Fax) Belthorn House Walker Rd mailto:mike.leach@arm.com Guide Blackburn BB1 2QE
-----Original Message----- From: Chunyan Zhang [mailto:zhang.chunyan@linaro.org] Sent: 27 January 2016 11:12 To: Mike Leach Cc: coresight@lists.linaro.org; Mathieu Poirier Subject: ATCLK on STM
Hi Mike,
The "Appendix A. CoreSight Port List" in [1] documents that many of CoreSight components have a clock signal called 'ATCLK', but I didn't see the description on STM ATCLK. So is there the 'ATCLK' signal on STM too? At what situations the CoreSight components need ATCLK?
Many thanks, Chunyan
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Cihejf ib.html
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