On Mon, 10 Jun 2019 at 23:31, Mathieu Poirier mathieu.poirier@linaro.org wrote:
On Wed, Jun 05, 2019 at 08:02:59PM +0100, Mike Leach wrote:
Adds sysfs access to the coresight management registers.
Signed-off-by: Mike Leach mike.leach@linaro.org
.../hwtracing/coresight/coresight-cti-sysfs.c | 49 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 50 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index deb882a6a367..ad7c45390313 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -66,9 +66,52 @@ static ssize_t enable_store(struct device *dev, } static DEVICE_ATTR_RW(enable);
+static ssize_t ctmid_show(struct device *dev,
struct device_attribute *attr,char *buf)+{
struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);return scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->ctidev.ctm_id);+} +static DEVICE_ATTR_RO(ctmid);
/* attribute and group sysfs tables. */ static struct attribute *coresight_cti_attrs[] = { &dev_attr_enable.attr,
&dev_attr_ctmid.attr,NULL,+};
+/* register based attributes */ +#define coresight_cti_reg(name, offset) \
coresight_simple_reg32(struct cti_drvdata, name, offset)+/* coresight management registers */ +coresight_cti_reg(devaff0, CTIDEVAFF0); +coresight_cti_reg(devaff1, CTIDEVAFF1); +coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS); +coresight_cti_reg(devarch, CORESIGHT_DEVARCH); +coresight_cti_reg(devid, CORESIGHT_DEVID); +coresight_cti_reg(devtype, CORESIGHT_DEVTYPE); +coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0); +coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1); +coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2); +coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3); +coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4);
Do we need the peripheral ID registers? Same for DEVARCH - I don't see it being used anywhere after this patch.
I prefer completeness - whoever is using the raw register access is likely to have the TRM - I don't wish to presume to know what some user may require. (as an aside - these regs are used in the AMBA layer to ID the CTI)
Thanks
Mike
With the above, Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
+static struct attribute *coresight_cti_mgmt_attrs[] = {
&dev_attr_devaff0.attr,&dev_attr_devaff1.attr,&dev_attr_authstatus.attr,&dev_attr_devarch.attr,&dev_attr_devid.attr,&dev_attr_devtype.attr,&dev_attr_pidr0.attr,&dev_attr_pidr1.attr,&dev_attr_pidr2.attr,&dev_attr_pidr3.attr,&dev_attr_pidr4.attr, NULL,};
@@ -76,7 +119,13 @@ static const struct attribute_group coresight_cti_group = { .attrs = coresight_cti_attrs, };
+static const struct attribute_group coresight_cti_mgmt_group = {
.attrs = coresight_cti_mgmt_attrs,.name = "mgmt",+};
const struct attribute_group *coresight_cti_groups[] = { &coresight_cti_group,
&coresight_cti_mgmt_group, NULL,}; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index dd2991dfbf4c..64a888cc620f 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -22,6 +22,7 @@ #define CORESIGHT_CLAIMCLR 0xfa4 #define CORESIGHT_LAR 0xfb0 #define CORESIGHT_LSR 0xfb4 +#define CORESIGHT_DEVARCH 0xfbc #define CORESIGHT_AUTHSTATUS 0xfb8 #define CORESIGHT_DEVID 0xfc8
#define CORESIGHT_DEVTYPE 0xfcc
2.20.1
CoreSight mailing list CoreSight@lists.linaro.org https://lists.linaro.org/mailman/listinfo/coresight
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK