Re: [RFC PATCH v2 10/13] drivers: dts: Add CTI options for qcom msm8916

Hi Leo,

On Sun, 26 May 2019 at 13:29, Leo Yan leo.yan@linaro.org wrote:

On Wed, May 01, 2019 at 09:49:42AM +0100, Mike Leach wrote:

...

Signed-off-by: Mike Leach mike.leach@linaro.org

arch/arm64/boot/dts/qcom/msm8916.dtsi | 102 +++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0803ca8c02da..86d0b185a207 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -16,6 +16,7 @@ #include <dt-bindings/reset/qcom,gcc-msm8916.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/arm/coresight-cti-dt.h>

/ { interrupt-parent = <&intc>; @@ -1352,7 +1353,7 @@ cpu = <&CPU3>; };

•         etm@85c000 {
  

•         etm0: etm@85c000 {
                  compatible = "arm,coresight-etm4x", "arm,primecell";
                  reg = <0x85c000 0x1000>;
  
  

@@ -1370,7 +1371,7 @@ }; };

•         etm@85d000 {
  

•         etm1: etm@85d000 {
                  compatible = "arm,coresight-etm4x", "arm,primecell";
                  reg = <0x85d000 0x1000>;
  
  

@@ -1388,7 +1389,7 @@ }; };

•         etm@85e000 {
  

•         etm2: etm@85e000 {
                  compatible = "arm,coresight-etm4x", "arm,primecell";
                  reg = <0x85e000 0x1000>;
  
  

@@ -1406,7 +1407,7 @@ }; };

•         etm@85f000 {
  

•         etm3: etm@85f000 {
                  compatible = "arm,coresight-etm4x", "arm,primecell";
                  reg = <0x85f000 0x1000>;
  
  

@@ -1424,6 +1425,99 @@ }; };

•         /* System CTIs */
  

•         /* CTI 0 - TMC connections */
  

•         cti@810000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x810000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•         };
  

•         /* CTI 1 - TPIU connections */
  

•         cti@811000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x811000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•         };
  

•         /* CTIs 2-11 - no information - not instantiated */
  

•         /* Core CTIs; CTIs 12-15 */
  

•         /* CTI - CPU-0 */
  

•         cti@858000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x858000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•                 arm,cti-v8-arch;
  

•                 cpu = <&CPU0>;
  

•                 arm,cs-dev-assoc = <&etm0>;
  

•         };
  

•         /* CTI - CPU-1 */
  

•         cti@859000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x859000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•                 arm,cti-v8-arch;
  

•                 cpu = <&CPU1>;
  

•                 arm,cs-dev-assoc = <&etm1>;
  

•         };
  

•         /* CTI - CPU-2 */
  

•         cti@85a000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x85a000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•                 /* v8 cpu the hard way... */
  

•                 trig-conns@0 {
  

+/* #address-cells = <1>;

•                              #size-cells = <0>;
  

•                              reg = <0>;*/
  

•                              cpu = <&CPU2>;
  

•                              arm,trig-in-sigs=<0 1>;
  

•                              arm,trig-in-types=<PE_DBGTRIGGER PE_PMUIRQ>;
  

•                              arm,trig-out-sigs=<0 1 2 >;
  

•                              arm,trig-out-types=<PE_EDBGREQ PE_DBGRESTART PE_CTIIRQ>;
  

•                              arm,trig-filters=<0>;
  

•                 };
  

•                 trig-conns@1 {
  

•                              /* reg = <1>; */
  

•                              arm,trig-in-sigs = <4 5 6 7>;
  

•                              arm,trig-in-types = <ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT ETM_EXTOUT>;
  

•                              arm,trig-out-sigs = <4 5 6 7>;
  

•                              arm,trig-out-types = <ETM_EXTIN ETM_EXTIN ETM_EXTIN ETM_EXTIN>;
  

•                              arm,cs-dev-assoc = <&etm2>;
  

•                 };
  

•         };
  

Should apply the same binding for CPU2 with other CPUs?

Yes - this was here for testing purposes - I missed changing it back. I'll reset it to a standard v8 binding next set

Thanks

Mike

...

•         /* CTI - CPU-3 */
  

•         cti@85b000 {
  

•                 compatible = "arm,coresight-cti", "arm,primecell";
  

•                 reg = <0x85b000 0x1000>;
  

•                 clocks = <&rpmcc RPM_QDSS_CLK>;
  

•                 clock-names = "apb_pclk";
  

•                 arm,cti-v8-arch;
  

•                 cpu = <&CPU3>;
  

•                 arm,cs-dev-assoc = <&etm3>;
  

•         };
  

•         venus: video-codec@1d00000 {
                  compatible = "qcom,msm8916-venus";
                  reg = <0x01d00000 0xff000>;
  

-- 2.20.1

---

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