Hi Leo,
On Sat, Mar 20, 2021 at 10:59:42AM +0800, Leo Yan wrote:
From: Georgi Djakov georgi.djakov@linaro.org
Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916, which can benefit the CoreSight development on DB410c.
Signed-off-by: Georgi Djakov georgi.djakov@linaro.org Signed-off-by: Leo Yan leo.yan@linaro.org
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3a9538e1ec97..dd87e5d739ab 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -406,6 +406,7 @@ &wcd_codec { &etm1 { status = "okay"; }; &etm2 { status = "okay"; }; &etm3 { status = "okay"; }; +&stm { status = "okay"; }; &etr { status = "okay"; }; &funnel0 { status = "okay"; }; &funnel1 { status = "okay"; };
This is alphabetically ordered so &stm should be on the line before &tpiu.
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..892f1772e53c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi [...] @@ -882,6 +889,26 @@ etm3_out: endpoint { }; };
stm: stm@802000 {
And these nodes are sorted by their unit address (0x802000), so stm@802000 should be the first coresight node, before cti@810000.
compatible = "arm,coresight-stm", "arm,primecell";reg = <0x802000 0x1000>,<0x9280000 0x180000>;
And please pad these addresses with zeroes so the order is more easily visible, i.e.
+ reg = <0x00802000 0x1000>, + <0x09280000 0x180000>;
Thanks! Stephan