On Wed, 20 Mar 2019 at 08:16, Suzuki K Poulose suzuki.poulose@arm.com wrote:
Hi Mathieu,
On 06/03/2019 22:57, Mathieu Poirier wrote:
This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink.
Signed-off-by: Mathieu Poirier mathieu.poirier@linaro.org
.../hwtracing/coresight/coresight-tmc-etr.c | 39 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.c | 2 + drivers/hwtracing/coresight/coresight-tmc.h | 3 ++ 3 files changed, 39 insertions(+), 5 deletions(-)
@@ -1463,10 +1468,32 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) goto unlock_out; }
/* Get a handle on the pid of the process to monitor */pid = etr_perf->etr_buf->pid;/* Do not proceed if this device is associated with another session */if (drvdata->pid != -1 && drvdata->pid != pid) {rc = -EBUSY;goto unlock_out;}etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); drvdata->perf_data = etr_perf;/** No HW configuration is needed if the sink is already in* use for this session.*/if (drvdata->pid == pid) {drvdata->mode = CS_MODE_PERF;minor nit: This is not needed ^^. Otherwise, looks good to me.
An astute observation - I will also fix it for ETF and ETB.
Mathieu
Suzuki