On 2021/4/19 19:17, Suzuki K Poulose wrote:
On 17/04/2021 11:17, Yicong Yang wrote:
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex integrated Endpoint (RCiEP) device, providing the capability to dynamically monitor and tune the PCIe traffic (tune), and trace the TLP headers (trace).
PTT tune is designed for monitoring and adjusting PCIe link parameters. We provide several parameters of the PCIe link. Through the driver, user can adjust the value of certain parameter to affect the PCIe link for the purpose of enhancing the performance in certian situation.
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The reason for not using perf is because there is no current support for uncore tracing in the perf facilities. We have our own format of data and don't need perf doing the parsing. The setting through perf tools doesn't seem to be friendly as well. For example, we cannot count on perf to decode the usual format BDF number like <domain>:<bus>:<dev>.<fn>, which user can use to filter the TLP headers through the PTT device.
A similar approach for implementing this function is ETM, which use sysfs for configuring and a character device for dumping data.
Greg has some comments on our implementation and doesn't advocate to build driver on debugfs [1]. So I resend this series to collect more feedbacks on the implementation of this driver.
Hi perf and ETM related experts, is it suggested to adapt this driver to perf? Or is the debugfs approach acceptable? Otherwise use sysfs + character device like ETM and use perf tools for decoding it? Any comments is welcomed.
Please use perf. Debugfs / sysfs is not the right place for these things.
ok.
Also, please move your driver to drivers/perf/
Does it make sense as it's a tuning and tracing device, and doesn't have counters nor do the sampling like usual PMU device under drivers/perf/.
As Alex mentioned, the ETM drivers were initially developed when the AUX buffer was not available. The sysfs interface is there only for the backward compatibility and for bring up ( due to the nature of the connections between the CoreSight components and sometimes the missing engineering spec).
got it. thanks for the explanation.
Regards, Yicong
Suzuki
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